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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Diff between revs 116 and 139

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Rev 116 Rev 139
Line 43... Line 43...
`ifdef DFF
`ifdef DFF
`define MODULE dff
`define MODULE dff
module `BASE`MODULE ( d, q, clk, rst);
module `BASE`MODULE ( d, q, clk, rst);
`undef MODULE
`undef MODULE
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = {width{1'b0}};
 
 
        input [width-1:0] d;
        input [width-1:0] d;
        input clk, rst;
        input clk, rst;
        output reg [width-1:0] q;
        output reg [width-1:0] q;
 
 
Line 93... Line 93...
`define MODULE dff_ce
`define MODULE dff_ce
module `BASE`MODULE ( d, ce, q, clk, rst);
module `BASE`MODULE ( d, ce, q, clk, rst);
`undef MODULE
`undef MODULE
 
 
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = {width{1'b0}};
 
 
        input [width-1:0] d;
        input [width-1:0] d;
        input ce, clk, rst;
        input ce, clk, rst;
        output reg [width-1:0] q;
        output reg [width-1:0] q;
 
 
Line 115... Line 115...
`define MODULE dff_ce_clear
`define MODULE dff_ce_clear
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
`undef MODULE
`undef MODULE
 
 
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = {width{1'b0}};
 
 
        input [width-1:0] d;
        input [width-1:0] d;
        input ce, clear, clk, rst;
        input ce, clear, clk, rst;
        output reg [width-1:0] q;
        output reg [width-1:0] q;
 
 
Line 140... Line 140...
`define MODULE dff_ce_set
`define MODULE dff_ce_set
module `BASE`MODULE ( d, ce, set, q, clk, rst);
module `BASE`MODULE ( d, ce, set, q, clk, rst);
`undef MODULE
`undef MODULE
 
 
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = {width{1'b0}};
 
 
        input [width-1:0] d;
        input [width-1:0] d;
        input ce, set, clk, rst;
        input ce, set, clk, rst;
        output reg [width-1:0] q;
        output reg [width-1:0] q;
 
 

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