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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Diff between revs 98 and 100

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Rev 98 Rev 100
Line 515... Line 515...
output reg q;
output reg q;
output clk, rst;
output clk, rst;
reg dff;
reg dff;
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
if (rst)
if (rst)
    {dff,q} <= 2'b00;
    {q,dff} <= 2'b00;
else
else
    {dff,q} <= {d,dff};
    {q,dff} <= {dff,d};
endmodule
endmodule
`endif
`endif
 
 
`ifdef CDC
`ifdef CDC
`define MODULE cdc
`define MODULE cdc
Line 553... Line 553...
    .rst(rst_dst));
    .rst(rst_dst));
 
 
`define MODULE toggle2pulse
`define MODULE toggle2pulse
`BASE`MODULE t2p0 (
`BASE`MODULE t2p0 (
`undef MODULE
`undef MODULE
    .d(take_it_sync),
    .d(take_it_tg_sync),
    .pl(take_it_pl),
    .pl(take_it_pl),
    .clk(clk_dst),
    .clk(clk_dst),
    .rst(rst_dst));
    .rst(rst_dst));
 
 
// dst -> src
// dst -> src
Line 578... Line 578...
    .rst(rst_src));
    .rst(rst_src));
 
 
`define MODULE toggle2pulse
`define MODULE toggle2pulse
`BASE`MODULE t2p1 (
`BASE`MODULE t2p1 (
`undef MODULE
`undef MODULE
    .d(take_it_grant_tg_sync),
    .d(got_it_tg_sync),
    .pl(got_it_pl),
    .pl(got_it_pl),
    .clk(clk_src),
    .clk(clk_src),
    .rst(rst_src));
    .rst(rst_src));
 
 
endmodule
endmodule

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