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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Diff between revs 15 and 17

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Rev 15 Rev 17
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     else
     else
       direction <= going_full;*/
       direction <= going_full;*/
endmodule
endmodule
`endif
`endif
 
 
 
module shreg ( d, q, clk, rst);
 
parameter depth = 10;
 
input d;
 
output q;
 
input clk, rst;
 
 
 
reg [1:depth] dffs;
 
 
 
always @ (posedge clk or posedge rst)
 
if (rst)
 
    dffs <= {depth{1'b0}};
 
else
 
    dffs <= {d,dffs[1:depth-1]};
 
assign q = dffs[depth];
 
endmodule
 
 
 
module shreg_ce ( d, ce, q, clk, rst);
 
parameter depth = 10;
 
input d, ce;
 
output q;
 
input clk, rst;
 
 
 
reg [1:depth] dffs;
 
 
 
always @ (posedge clk or posedge rst)
 
if (rst)
 
    dffs <= {depth{1'b0}};
 
else
 
    if (ce)
 
        dffs <= {d,dffs[1:depth-1]};
 
assign q = dffs[depth];
 
endmodule
 
 
module delay ( d, q, clk, rst);
module delay ( d, q, clk, rst);
parameter depth = 10;
parameter depth = 10;
input d;
input d;
output q;
output q;
input clk, rst;
input clk, rst;
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    dffs <= {depth{1'b0}};
    dffs <= {depth{1'b0}};
else
else
    dffs <= {d,dffs[1:depth-1]};
    dffs <= {d,dffs[1:depth-1]};
assign q = dffs[depth];
assign q = dffs[depth];
endmodule
endmodule
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module delay_emptyflag ( d, q, emptyflag, clk, rst);
 
parameter depth = 10;
 
input d;
 
output q, emptyflag;
 
input clk, rst;
 
 
 
reg [1:depth] dffs;
 
 
 
always @ (posedge clk or posedge rst)
 
if (rst)
 
    dffs <= {depth{1'b0}};
 
else
 
    dffs <= {d,dffs[1:depth-1]};
 
assign q = dffs[depth];
 
assign emptyflag = !(|dffs);
 
endmodule
 
 
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