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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Diff between revs 29 and 40

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Rev 29 Rev 40
Line 38... Line 38... 
//// Public License along with this source; if not, download it   ////
 
//// Public License along with this source; if not, download it   ////
 
//// from http://www.opencores.org/lgpl.shtml                     ////
 
//// from http://www.opencores.org/lgpl.shtml                     ////
 
////                                                              ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
 
 
 
 
module vl_dff ( d, q, clk, rst);
 
`ifdef DFF
 
 
 
`define MODULE dff
 
 
 
module `BASE`MODULE ( d, q, clk, rst);
 
 
 
`undef MODULE
 
        parameter width = 1;
 
        parameter width = 1;
 
        parameter reset_value = 0;
 
        parameter reset_value = 0;
 
 
 
 
 
        input [width-1:0] d;
 
        input [width-1:0] d;
 
        input clk, rst;
 
        input clk, rst;
Line 54... Line 56... 
                q <= reset_value;
 
                q <= reset_value;
 
        else
 
        else
 
                q <= d;
 
                q <= d;
 
 
 
 
 
endmodule
 
endmodule
 
 
 
`endif
 
 
 
 
 
module vl_dff_array ( d, q, clk, rst);
 
`ifdef DFF_ARRAY
 
 
 
`define MODULE dff_array
 
 
 
module `BASE`MODULE ( d, q, clk, rst);
 
 
 
`undef MODULE
 
 
 
 
 
        parameter width = 1;
 
        parameter width = 1;
 
        parameter depth = 2;
 
        parameter depth = 2;
 
        parameter reset_value = 1'b0;
 
        parameter reset_value = 1'b0;
 
 
 
 
Line 79... Line 85... 
        end
 
        end
 
 
 
 
 
    assign q = q_tmp[depth-1];
 
    assign q = q_tmp[depth-1];
 
 
 
 
 
endmodule
 
endmodule
 
 
 
`endif
 
 
 
 
 
module vl_dff_ce ( d, ce, q, clk, rst);
 
`ifdef DFF_CE
 
 
 
`define MODULE dff_ce
 
 
 
module `BASE`MODULE ( d, ce, q, clk, rst);
 
 
 
`undef MODULE
 
 
 
 
 
        parameter width = 1;
 
        parameter width = 1;
 
        parameter reset_value = 0;
 
        parameter reset_value = 0;
 
 
 
 
 
        input [width-1:0] d;
 
        input [width-1:0] d;
Line 97... Line 107... 
        else
 
        else
 
                if (ce)
 
                if (ce)
 
                        q <= d;
 
                        q <= d;
 
 
 
 
 
endmodule
 
endmodule
 
 
 
`endif
 
 
 
 
 
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
 
`ifdef DFF_CE_CLEAR
 
 
 
`define MODULE dff_ce_clear
 
 
 
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
 
 
 
`undef MODULE
 
 
 
 
 
        parameter width = 1;
 
        parameter width = 1;
 
        parameter reset_value = 0;
 
        parameter reset_value = 0;
 
 
 
 
 
        input [width-1:0] d;
 
        input [width-1:0] d;
Line 118... Line 132... 
                    q <= {width{1'b0}};
 
                    q <= {width{1'b0}};
 
                else
 
                else
 
                    q <= d;
 
                    q <= d;
 
 
 
 
 
endmodule
 
endmodule
 
 
 
`endif
 
 
 
 
 
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
 
`ifdef DF_CE_SET
 
 
 
`define MODULE dff_ce_set
 
 
 
module `BASE`MODULE ( d, ce, set, q, clk, rst);
 
 
 
`undef MODULE
 
 
 
 
 
        parameter width = 1;
 
        parameter width = 1;
 
        parameter reset_value = 0;
 
        parameter reset_value = 0;
 
 
 
 
 
        input [width-1:0] d;
 
        input [width-1:0] d;
Line 139... Line 157... 
                    q <= {width{1'b1}};
 
                    q <= {width{1'b1}};
 
                else
 
                else
 
                    q <= d;
 
                    q <= d;
 
 
 
 
 
endmodule
 
endmodule
 
 
 
`endif
 
 
 
 
 
module vl_spr ( sp, r, q, clk, rst);
 
`ifdef SPR
 
 
 
`define MODULE spr
 
 
 
module `BASE`MODULE ( sp, r, q, clk, rst);
 
 
 
`undef MODULE
 
 
 
 
 
        parameter width = 1;
 
        parameter width = 1;
 
        parameter reset_value = 0;
 
        parameter reset_value = 0;
 
 
 
 
 
        input sp, r;
 
        input sp, r;
Line 159... Line 181... 
                q <= 1'b1;
 
                q <= 1'b1;
 
            else if (r)
 
            else if (r)
 
                q <= 1'b0;
 
                q <= 1'b0;
 
 
 
 
 
endmodule
 
endmodule
 
 
 
`endif
 
 
 
 
 
module vl_srp ( s, rp, q, clk, rst);
 
`ifdef SRP
 
 
 
`define MODULE srp
 
 
 
module `BASE`MODULE ( s, rp, q, clk, rst);
 
 
 
`undef MODULE
 
 
 
 
 
        parameter width = 1;
 
        parameter width = 1;
 
        parameter reset_value = 0;
 
        parameter reset_value = 0;
 
 
 
 
 
        input s, rp;
 
        input s, rp;
Line 179... Line 205... 
                q <= 1'b0;
 
                q <= 1'b0;
 
            else if (s)
 
            else if (s)
 
                q <= 1'b1;
 
                q <= 1'b1;
 
 
 
 
 
endmodule
 
endmodule
 
 
 
`endif
 
 
 
 
 
`ifdef ALTERA
 
`ifdef ALTERA
 
 
 
 
 
 
 
`ifdef DFF_SR
 
// megafunction wizard: %LPM_FF%
 
// megafunction wizard: %LPM_FF%
 
// GENERATION: STANDARD
 
// GENERATION: STANDARD
 
// VERSION: WM1.0
 
// VERSION: WM1.0
 
// MODULE: lpm_ff 
// MODULE: lpm_ff 
 
 
 
Line 220... Line 248... 
 
 
 
 
 
 
 
 
// synopsys translate_off
 
// synopsys translate_off
 
`timescale 1 ps / 1 ps
 
`timescale 1 ps / 1 ps
 
// synopsys translate_on
 
// synopsys translate_on
 
module vl_dff_sr (
 
`define MODULE dff_sr
 
 
 
module `BASE`MODULE (
 
 
 
`undef MODULE
 
 
 
 
 
        aclr,
 
        aclr,
 
        aset,
 
        aset,
 
        clock,
 
        clock,
 
        data,
 
        data,
 
        q);
 
        q);
Line 300... Line 331... 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
 
// Retrieval info: LIB_FILE: lpm
 
// Retrieval info: LIB_FILE: lpm
 
 
 
`endif
 
 
 
 
 
`else
 
`else
 
 
 
 
 
 
 
`ifdef DFF_SR
 
module vl_dff_sr ( aclr, aset, clock, data, q);
 
`define MODULE dff_sr
 
 
 
module `BASE`MODULE ( aclr, aset, clock, data, q);
 
 
 
`undef MODULE
 
 
 
 
 
    input         aclr;
 
    input         aclr;
 
    input         aset;
 
    input         aset;
 
    input         clock;
 
    input         clock;
 
    input         data;
 
    input         data;
Line 322... Line 355... 
       q <= 1'b1;
 
       q <= 1'b1;
 
     else
 
     else
 
       q <= data;
 
       q <= data;
 
 
 
 
 
endmodule
 
endmodule
 
 
 
`endif
 
 
 
 
 
`endif
 
`endif
 
 
 
 
 
// LATCH
 
// LATCH
 
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
 
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
 
`ifdef ALTERA
 
`ifdef ALTERA
 
module vl_latch ( d, le, q, clk);
 
 
 
 
 
`ifdef LATCH
 
 
 
`define MODULE latch
 
 
 
module `BASE`MODULE ( d, le, q, clk);
 
 
 
`undef MODULE
 
input d, le;
 
input d, le;
 
output q;
 
output q;
 
input clk;
 
input clk;
 
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
 
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
 
endmodule
 
endmodule
 
 
 
`endif
 
 
 
 
 
`else
 
`else
 
module latch ( d, le, q, clk);
 
 
 
 
 
`ifdef LATCH
 
 
 
`define MODULE latch
 
 
 
module `BASE`MODULE ( d, le, q, clk);
 
 
 
`undef MODULE
 
input d, le;
 
input d, le;
 
output q;
 
output q;
 
input clk;/*
 
input clk;/*
 
   always @ (posedge direction_set or posedge direction_clr)
 
   always @ (posedge direction_set or posedge direction_clr)
 
     if (direction_clr)
 
     if (direction_clr)
Line 347... Line 391... 
     else
 
     else
 
       direction <= going_full;*/
 
       direction <= going_full;*/
 
endmodule
 
endmodule
 
`endif
 
`endif
 
 
 
 
 
module vl_shreg ( d, q, clk, rst);
 
`endif
 
 
 
 
 
 
 
`ifdef SHREG
 
 
 
`define MODULE shreg
 
 
 
module `BASE`MODULE ( d, q, clk, rst);
 
 
 
`undef MODULE
 
 
 
 
 
parameter depth = 10;
 
parameter depth = 10;
 
input d;
 
input d;
 
output q;
 
output q;
 
input clk, rst;
 
input clk, rst;
 
 
 
 
Line 362... Line 412... 
    dffs <= {depth{1'b0}};
 
    dffs <= {depth{1'b0}};
 
else
 
else
 
    dffs <= {d,dffs[1:depth-1]};
 
    dffs <= {d,dffs[1:depth-1]};
 
assign q = dffs[depth];
 
assign q = dffs[depth];
 
endmodule
 
endmodule
 
 
 
`endif
 
 
 
 
 
module vl_shreg_ce ( d, ce, q, clk, rst);
 
`ifdef SHREG_CE
 
 
 
`define MODULE shreg_ce
 
 
 
module `BASE`MODULE ( d, ce, q, clk, rst);
 
 
 
`undef MODULE
 
parameter depth = 10;
 
parameter depth = 10;
 
input d, ce;
 
input d, ce;
 
output q;
 
output q;
 
input clk, rst;
 
input clk, rst;
 
 
 
 
Line 379... Line 433... 
else
 
else
 
    if (ce)
 
    if (ce)
 
        dffs <= {d,dffs[1:depth-1]};
 
        dffs <= {d,dffs[1:depth-1]};
 
assign q = dffs[depth];
 
assign q = dffs[depth];
 
endmodule
 
endmodule
 
 
 
`endif
 
 
 
 
 
module vl_delay ( d, q, clk, rst);
 
`ifdef DELAY
 
 
 
`define MODULE delay
 
 
 
module `BASE`MODULE ( d, q, clk, rst);
 
 
 
`undef MODULE
 
parameter depth = 10;
 
parameter depth = 10;
 
input d;
 
input d;
 
output q;
 
output q;
 
input clk, rst;
 
input clk, rst;
 
 
 
 
Line 395... Line 453... 
    dffs <= {depth{1'b0}};
 
    dffs <= {depth{1'b0}};
 
else
 
else
 
    dffs <= {d,dffs[1:depth-1]};
 
    dffs <= {d,dffs[1:depth-1]};
 
assign q = dffs[depth];
 
assign q = dffs[depth];
 
endmodule
 
endmodule
 
 
 
`endif
 
 
 
 
 
 
 
`ifdef DELAY_EMPTYFLAG
 
 
 
`define MODULE delay_emptyflag
 
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
 
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
 
 
 
`undef MODULE
 
parameter depth = 10;
 
parameter depth = 10;
 
input d;
 
input d;
 
output q, emptyflag;
 
output q, emptyflag;
 
input clk, rst;
 
input clk, rst;
 
 
 
 
Line 412... Line 474... 
else
 
else
 
    dffs <= {d,dffs[1:depth-1]};
 
    dffs <= {d,dffs[1:depth-1]};
 
assign q = dffs[depth];
 
assign q = dffs[depth];
 
assign emptyflag = !(|dffs);
 
assign emptyflag = !(|dffs);
 
endmodule
 
endmodule
 
 
 
`endif
 
 
 
 
 
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