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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Diff between revs 40 and 41

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Line 457... Line 457...
endmodule
endmodule
`endif
`endif
 
 
`ifdef DELAY_EMPTYFLAG
`ifdef DELAY_EMPTYFLAG
`define MODULE delay_emptyflag
`define MODULE delay_emptyflag
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
`undef MODULE
`undef MODULE
parameter depth = 10;
parameter depth = 10;
input d;
input d;
output q, emptyflag;
output q, emptyflag;
input clk, rst;
input clk, rst;

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