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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Diff between revs 48 and 60

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Rev 48 Rev 60
Line 383... Line 383...
module `BASE`MODULE ( d, le, q, clk);
module `BASE`MODULE ( d, le, q, clk);
`undef MODULE
`undef MODULE
input d, le;
input d, le;
input clk;
input clk;
always @ (le or d)
always @ (le or d)
if le
if (le)
    d <= q;
    d <= q;
endmodule
endmodule
`endif
`endif
 
 
`endif
`endif

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