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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Diff between revs 75 and 94

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Rev 75 Rev 94
Line 473... Line 473...
assign q = dffs[depth];
assign q = dffs[depth];
assign emptyflag = !(|dffs);
assign emptyflag = !(|dffs);
endmodule
endmodule
`endif
`endif
 
 
`ifdef ASYNC_REG_REQ_ACK
`ifdef PULSE2TOGGLE
`define MODULE async_reg_req_ack
`define MODULE pules2toggle
module `BASE`MODULE ( d, q, req_i, req_o, ack_i, ack_o, clk_a, rst_a, clk_b, rst_b);
module `BASE`MODULE ( pl, q, clk, rst)
`undef MODULE
`undef MODULE
parameter data_width = 8;
input pl;
input [data_width-1:0] d;
output q;
output [data_width-1:0] q;
input clk, rst;
input req_i;
input
output req_o;
always @ (posedge clk or posedge rst)
input ack_i;
if (rst)
output ack_o;
    q <= 1'b0;
input clk_a, rst_a, clk_b, rst_b;
 
 
 
reg [3:0] reqi; // 3: last req in clk_a, 2: input dff, 1-0: sync
 
wire rst;
 
 
 
always @ (posedge clk_a or rst_a)
 
if (rst_a)
 
    q <= {data_width{1'b0}};
 
else
else
    if (req_i)
    q <= pl ^ q;
        q <= d;
endmodule
 
`endif
 
 
assign rst = ack_i | rst_a;
`ifdef TOGGLE2PULSE
always @ (posedge clk_a or posedge rst)
`define MODULE toggle2pulse;
 
module `BASE`MODULE (d, pl, clk, rst);
 
input d;
 
output pl;
 
input clk, rst;
 
reg dff;
 
always @ (posedge clk or posedge rst)
if (rst)
if (rst)
    req[2] <= 1'b0;
    dff <= 1'b0;
else
else
    req[2] <= req_i & !ack_o;
    dff <= d;
 
assign d ^ dff;
 
endmodule
 
`endif
 
 
always @ (posedge clk_a or posedge rst_a)
`ifdef SYNCHRONIZER
if (rst_a)
`define MODULE synchronizer
    req[3] <= 1'b0;
module `BASE`MODULE (d, q, clk, rst);
 
`undef MODULE
 
input d;
 
output reg q;
 
output clk, rst;
 
reg dff;
 
always @ (posedge clk or posedge rst)
 
if (rst)
 
    {dff,q} <= 2'b00;
else
else
    req[3] <= req[2];
    {dff,q} <= {d,dff};
 
endmodule
 
`endif
 
 
always @ (posedge clk_b or posedge rst_b)
`ifdef CDC
if (rst_b)
`define MODULE cdc
    req[1:0] <= 2'b00;
module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst)
else
`undef MODULE
    if (ack_i)
input start_pl;
        req[1:0] <= 2'b00;
output take_it_pl;
    else
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
        req[1:0] <= req[2:1];
output got_it_pl;
assign req_o = req[0];
input clk_src, rst_src;
 
input clk_dst, rst_dst;
 
wire take_it_tg, take_it_tg_sync;
 
wire got_it_tg, got_it_tg_sync;
 
// src -> dst
 
`define MODULE pulse2toggle
 
`BASE`MODULE p2t0 (
 
`undef MODULE
 
    .pl(start_pl),
 
    .q(take_it_tg),
 
    .clk(clk_src),
 
    .rst(rst_src));
 
 
always @ (posedge clk_a or posedge rst_a)
`define MODULE synchronizer
if (rst_a)
`BASE`MODULE sync0 (
    ack_o <= 1'b0;
`undef MODULE
else
    .d(take_it_tg),
    ack_o <= req[3] & req[2];
    .q(take_it_tg_sync),
 
    .clk(clk_dst),
 
    .rst(rst_dst));
 
 
 
`define MODULE toggle2pulse
 
`BASE`MODULE t2p0 (
 
`undef MODULE
 
    .d(take_it_sync),
 
    .pl(take_it_pl),
 
    .clk(clk_dst),
 
    .rst(rst_dst));
 
 
 
// dst -> src
 
`define MODULE pulse2toggle
 
`BASE`MODULE p2t0 (
 
`undef MODULE
 
    .pl(take_it_grant_pl),
 
    .q(got_it_tg),
 
    .clk(clk_dst),
 
    .rst(rst_dst));
 
 
 
`define MODULE synchronizer
 
`BASE`MODULE sync1 (
 
`undef MODULE
 
    .d(got_it_tg),
 
    .q(got_it_tg_sync),
 
    .clk(clk_src),
 
    .rst(rst_src));
 
 
 
`define MODULE toggle2pulse
 
`BASE`MODULE t2p1 (
 
`undef MODULE
 
    .d(take_it_grant_tg_sync),
 
    .pl(got_it_pl),
 
    .clk(clk_src),
 
    .rst(rst_src));
 
 
endmodule
endmodule
`endif
`endif
 
 
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