URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Diff between revs 94 and 97

Rev 94	Rev 97
Line 492...	Line 492...
`endif	`endif

`ifdef TOGGLE2PULSE	`ifdef TOGGLE2PULSE
`define MODULE toggle2pulse;	`define MODULE toggle2pulse;
module `BASE`MODULE (d, pl, clk, rst);	module `BASE`MODULE (d, pl, clk, rst);
	`undef MODULE
`input d;`	`input d;`
`output pl;`	`output pl;`
`input clk, rst;`	`input clk, rst;`
`reg dff;`	`reg dff;`
`always @ (posedge clk or posedge rst)`	`always @ (posedge clk or posedge rst)`
Line 523...	Line 524...
`endmodule`	`endmodule`
`endif	`endif

`ifdef CDC	`ifdef CDC
`define MODULE cdc	`define MODULE cdc
module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst)	module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
`undef MODULE	`undef MODULE
`input start_pl;`	`input start_pl;`
`output take_it_pl;`	`output take_it_pl;`
`input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack`	`input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack`
`output got_it_pl;`	`output got_it_pl;`