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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Diff between revs 97 and 98

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Rev 97 Rev 98
Line 474... Line 474...
assign emptyflag = !(|dffs);
assign emptyflag = !(|dffs);
endmodule
endmodule
`endif
`endif
 
 
`ifdef PULSE2TOGGLE
`ifdef PULSE2TOGGLE
`define MODULE pules2toggle
`define MODULE pulse2toggle
module `BASE`MODULE ( pl, q, clk, rst)
module `BASE`MODULE ( pl, q, clk, rst);
`undef MODULE
`undef MODULE
input pl;
input pl;
output q;
output reg q;
input clk, rst;
input clk, rst;
input
 
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
if (rst)
if (rst)
    q <= 1'b0;
    q <= 1'b0;
else
else
    q <= pl ^ q;
    q <= pl ^ q;
endmodule
endmodule
`endif
`endif
 
 
`ifdef TOGGLE2PULSE
`ifdef TOGGLE2PULSE
`define MODULE toggle2pulse;
`define MODULE toggle2pulse
module `BASE`MODULE (d, pl, clk, rst);
module `BASE`MODULE (d, pl, clk, rst);
`undef MODULE
`undef MODULE
input d;
input d;
output pl;
output pl;
input clk, rst;
input clk, rst;
Line 502... Line 501...
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
if (rst)
if (rst)
    dff <= 1'b0;
    dff <= 1'b0;
else
else
    dff <= d;
    dff <= d;
assign d ^ dff;
assign pl = d ^ dff;
endmodule
endmodule
`endif
`endif
 
 
`ifdef SYNCHRONIZER
`ifdef SYNCHRONIZER
`define MODULE synchronizer
`define MODULE synchronizer
Line 561... Line 560...
    .clk(clk_dst),
    .clk(clk_dst),
    .rst(rst_dst));
    .rst(rst_dst));
 
 
// dst -> src
// dst -> src
`define MODULE pulse2toggle
`define MODULE pulse2toggle
`BASE`MODULE p2t0 (
`BASE`MODULE p2t1 (
`undef MODULE
`undef MODULE
    .pl(take_it_grant_pl),
    .pl(take_it_grant_pl),
    .q(got_it_tg),
    .q(got_it_tg),
    .clk(clk_dst),
    .clk(clk_dst),
    .rst(rst_dst));
    .rst(rst_dst));

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