| Line 6044... |
Line 6044... |
localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
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localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
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parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
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parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
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parameter max_burst_width_a = 4;
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parameter max_burst_width_a = 4;
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parameter max_burst_width_b = max_burst_width_a;
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parameter max_burst_width_b = max_burst_width_a;
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parameter mode = "B3";
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parameter mode = "B3";
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parameter memory_init = 0;
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parameter memory_file = "vl_ram.v";
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input [data_width_a-1:0] wbsa_dat_i;
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input [data_width_a-1:0] wbsa_dat_i;
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input [addr_width_a-1:0] wbsa_adr_i;
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input [addr_width_a-1:0] wbsa_adr_i;
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input [data_width_a/8-1:0] wbsa_sel_i;
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input [data_width_a/8-1:0] wbsa_sel_i;
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input [2:0] wbsa_cti_i;
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input [2:0] wbsa_cti_i;
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input [1:0] wbsa_bte_i;
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input [1:0] wbsa_bte_i;
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input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
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input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
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output [data_width_a-1:0] wbsa_dat_o;
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output [data_width_a-1:0] wbsa_dat_o;
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output reg wbsa_ack_o;
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output wbsa_ack_o;
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output wbsa_stall_o;
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output wbsa_stall_o;
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input wbsa_clk, wbsa_rst;
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input wbsa_clk, wbsa_rst;
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input [data_width_b-1:0] wbsb_dat_i;
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input [data_width_b-1:0] wbsb_dat_i;
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input [addr_width_b-1:0] wbsb_adr_i;
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input [addr_width_b-1:0] wbsb_adr_i;
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input [data_width_b/8-1:0] wbsb_sel_i;
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input [data_width_b/8-1:0] wbsb_sel_i;
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input [2:0] wbsb_cti_i;
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input [2:0] wbsb_cti_i;
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input [1:0] wbsb_bte_i;
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input [1:0] wbsb_bte_i;
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input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
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input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
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output [data_width_b-1:0] wbsb_dat_o;
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output [data_width_b-1:0] wbsb_dat_o;
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output reg wbsb_ack_o;
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output wbsb_ack_o;
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output wbsb_stall_o;
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output wbsb_stall_o;
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input wbsb_clk, wbsb_rst;
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input wbsb_clk, wbsb_rst;
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wire [addr_width_a-1:0] adr_a;
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wire [addr_width_a-1:0] adr_a;
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wire [addr_width_b-1:0] adr_b;
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wire [addr_width_b-1:0] adr_b;
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| Line 6098... |
Line 6100... |
.clk(wbsb_clk),
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.clk(wbsb_clk),
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.rst(wbsb_rst));
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.rst(wbsb_rst));
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`undef MODULE
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`undef MODULE
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assign we_b = wbsb_we_i & wbsb_ack_o;
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assign we_b = wbsb_we_i & wbsb_ack_o;
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end else if (mode=="B4") begin : b4_inst
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end else if (mode=="B4") begin : b4_inst
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always @ (posedge wbsa_clk or posedge wbsa_rst)
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`define MODULE dff
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if (wbsa_rst)
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`BASE`MODULE dffacka ( .d(wbsa_stb_i & wbsa_cyc_i), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
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wbsa_ack_o <= 1'b0;
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else
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wbsa_ack_o <= wbsa_stb_i & wbsa_cyc_i;
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assign wbsa_stall_o = 1'b0;
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assign wbsa_stall_o = 1'b0;
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assign we_a = wbsa_we_i & wbsa_cyc_i & wbsa_stb_i;
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assign we_a = wbsa_we_i & wbsa_cyc_i & wbsa_stb_i;
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always @ (posedge wbsb_clk or posedge wbsb_rst)
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`BASE`MODULE dffackb ( .d(wbsb_stb_i & wbsb_cyc_i), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
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if (wbsb_rst)
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`undef MODULE
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wbsb_ack_o <= 1'b0;
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else
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wbsb_ack_o <= wbsb_stb_i & wbsb_cyc_i;
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assign wbsb_stall_o = 1'b0;
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assign wbsb_stall_o = 1'b0;
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assign we_b = wbsb_we_i & wbsb_cyc_i & wbsb_stb_i;
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assign we_b = wbsb_we_i & wbsb_cyc_i & wbsb_stb_i;
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end
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end
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endgenerate
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endgenerate
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`define MODULE dpram_be_2r2w
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`define MODULE dpram_be_2r2w
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`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size))
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`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size),
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.b_data_width(data_width_b), .b_addr_width(addr_width_b),
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.memory_init(memory_init), .memory_file(memory_file))
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`undef MODULE
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`undef MODULE
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ram_i (
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ram_i (
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.d_a(wbsa_dat_i),
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.d_a(wbsa_dat_i),
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.q_a(wbsa_dat_o),
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.q_a(wbsa_dat_o),
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.adr_a(adr_a),
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.adr_a(adr_a),
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