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// FIFO
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// FIFO
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module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
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module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
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parameter ADDR_WIDTH = 4;
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parameter addr_width = 4;
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parameter N = ADDR_WIDTH-1;
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parameter N = addr_width-1;
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parameter Q1 = 2'b00;
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parameter Q1 = 2'b00;
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parameter Q2 = 2'b01;
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parameter Q2 = 2'b01;
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parameter Q3 = 2'b11;
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parameter Q3 = 2'b11;
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parameter Q4 = 2'b10;
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parameter Q4 = 2'b10;
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// mux read or write adr to DPRAM
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// mux read or write adr to DPRAM
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assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
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assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
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assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
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assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
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vl_dp_ram_2r2w
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vl_dpram_2r2w
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# (.data_width(data_width), .addr_width(addr_width+1))
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# (.data_width(data_width), .addr_width(addr_width+1))
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dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
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dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
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.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
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.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
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vl_fifo_async_cmp
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vl_fifo_cmp_async
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# (.addr_width(addr_width))
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# (.addr_width(addr_width))
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cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
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cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
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vl_fifo_async_cmp
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vl_fifo_cmp_async
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# (.addr_width(addr_width))
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# (.addr_width(addr_width))
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cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
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cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
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endmodule
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endmodule
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