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Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Diff between revs 113 and 114

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Rev 113	Rev 114
Line 114...	Line 114...
`ifndef DPRAM_BE_2R2W	`ifndef DPRAM_BE_2R2W
`define DPRAM_BE_2R2W	`define DPRAM_BE_2R2W
`endif	`endif
`endif	`endif

`ifdef WB_RAM
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef RAM_BE
`define RAM_BE
`endif
`endif

`ifdef WB3_ARBITER_TYPE1	`ifdef WB3_ARBITER_TYPE1
`ifndef SPR	`ifndef SPR
`define SPR	`define SPR
`endif	`endif
`ifndef MUX_ANDOR	`ifndef MUX_ANDOR
Line 169...	Line 160...
`ifndef WB_AVALON_BRIDGE	`ifndef WB_AVALON_BRIDGE
`define WB_AVALON_BRIDGE	`define WB_AVALON_BRIDGE
`endif	`endif
`endif	`endif

`ifdef WB_SHADOW_RAM
`ifndef WB_RAM_BE
`define WB_RAM_BE
`endif
`endif

`ifdef WB_CACHE	`ifdef WB_CACHE
`ifndef RAM	`ifndef RAM
`define RAM	`define RAM
`endif	`endif
`ifndef WB_ADR_INC	`ifndef WB_ADR_INC
Line 197...	Line 182...
`define CDC	`define CDC
`endif	`endif
`endif	`endif

`ifdef WB_SHADOW_RAM	`ifdef WB_SHADOW_RAM
`ifndef WB_RAM	`ifndef WB_RAM_BE
`define WB_RAM	`define WB_RAM_BE
`endif	`endif
`endif	`endif

`ifdef WB_RAM	`ifdef WB_RAM
`ifndef WB_ADR_INC	`ifndef WB_ADR_INC
`define WB_ADR_INC	`define WB_ADR_INC
`endif	`endif
	`ifndef RAM_BE
	`define RAM_BE
	`endif
`endif	`endif

`ifdef MULTS18X18	`ifdef MULTS18X18
`ifndef MULTS	`ifndef MULTS
`define MULTS	`define MULTS

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