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`ifndef BASE
`ifndef BASE
`define BASE vl_
`define BASE vl_
`endif
`endif
 
 
// default SYN_KEEP definition
// default SYN_KEEP definition
`define SYN_KEEP /*synthesis syn_keep = 1*/
`define SYN_KEEP /*synthesis syn_keep = 1*/
 
 
`ifdef ACTEL
`ifdef ACTEL
`undef SYN_KEEP
`undef SYN_KEEP
`define SYN_KEEP /*synthesis syn_keep = 1*/
`define SYN_KEEP /*synthesis syn_keep = 1*/
`endif
`endif
 
 
`ifdef ACTEL
`ifdef ACTEL
    // ACTEL FPGA should not use logic to handle rw collision
    // ACTEL FPGA should not use logic to handle rw collision
    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
`else
`else
    `define SYN_NO_RW_CHECK
    `define SYN_NO_RW_CHECK
`endif
`endif
 
 
`ifdef ALL
`ifdef ALL
 
 
`define GBUF
`define GBUF
`define SYNC_RST
`define SYNC_RST
`define PLL
`define PLL
 
 
`define MULTS
`define MULTS
`define MULTS18X18
`define MULTS18X18
`define MULT
`define MULT
`define SHIFT_UNIT_32
`define SHIFT_UNIT_32
`define LOGIC_UNIT
`define LOGIC_UNIT
 
 
`define CNT_SHREG_WRAP
`define CNT_SHREG_WRAP
`define CNT_SHREG_CE_WRAP
`define CNT_SHREG_CE_WRAP
`define CNT_SHREG_CLEAR
`define CNT_SHREG_CLEAR
`define CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR_WRAP
`define CNT_SHREG_CE_CLEAR_WRAP
 
 
`define MUX_ANDOR
`define MUX_ANDOR
`define MUX2_ANDOR
`define MUX2_ANDOR
`define MUX3_ANDOR
`define MUX3_ANDOR
`define MUX4_ANDOR
`define MUX4_ANDOR
`define MUX5_ANDOR
`define MUX5_ANDOR
`define MUX6_ANDOR
`define MUX6_ANDOR
`define PARITY
`define PARITY
 
 
`define ROM_INIT
`define ROM_INIT
`define RAM
`define RAM
`define RAM_BE
`define RAM_BE
`define DPRAM_1R1W
`define DPRAM_1R1W
`define DPRAM_2R1W
`define DPRAM_2R1W
`define DPRAM_1R2W
`define DPRAM_1R2W
`define DPRAM_2R2W
`define DPRAM_2R2W
`define DPRAM_BE_2R2W
`define DPRAM_BE_2R2W
`define FIFO_1R1W_FILL_LEVEL_SYNC
`define FIFO_1R1W_FILL_LEVEL_SYNC
`define FIFO_2R2W_SYNC_SIMPLEX
`define FIFO_2R2W_SYNC_SIMPLEX
`define FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`define FIFO_1R1W_ASYNC
`define FIFO_1R1W_ASYNC
`define FIFO_2R2W_ASYNC
`define FIFO_2R2W_ASYNC
`define FIFO_2R2W_ASYNC_SIMPLEX
`define FIFO_2R2W_ASYNC_SIMPLEX
`define REG_FILE
`define REG_FILE
 
 
`define DFF
`define DFF
`define DFF_ARRAY
`define DFF_ARRAY
`define DFF_CE
`define DFF_CE
`define DFF_CE_CLEAR
`define DFF_CE_CLEAR
`define DF_CE_SET
`define DF_CE_SET
`define SPR
`define SPR
`define SRP
`define SRP
`define DFF_SR
`define DFF_SR
`define LATCH
`define LATCH
`define SHREG
`define SHREG
`define SHREG_CE
`define SHREG_CE
`define DELAY
`define DELAY
`define DELAY_EMPTYFLAG
`define DELAY_EMPTYFLAG
`define PULSE2TOGGLE
`define PULSE2TOGGLE
`define TOGGLE2PULSE
`define TOGGLE2PULSE
`define SYNCHRONIZER
`define SYNCHRONIZER
`define CDC
`define CDC
 
 
`define WB3AVALON_BRIDGE
`define WB3AVALON_BRIDGE
`define WB3WB3_BRIDGE
`define WB3WB3_BRIDGE
`define WB3_ARBITER_TYPE1
`define WB3_ARBITER_TYPE1
`define WB_ADR_INC
`define WB_ADR_INC
`define WB_RAM
`define WB_RAM
`define WB_SHADOW_RAM
`define WB_SHADOW_RAM
`define WB_B4_ROM
`define WB_B4_ROM
`define WB_BOOT_ROM
`define WB_BOOT_ROM
`define WB_DPRAM
`define WB_DPRAM
`define WB_CACHE
`define WB_CACHE
`define WB_AVALON_BRIDGE
`define WB_AVALON_BRIDGE
`define WB_AVALON_MEM_CACHE
`define WB_AVALON_MEM_CACHE
 
 
`define IO_DFF_OE
`define IO_DFF_OE
`define O_DFF
`define O_DFF
 
 
`endif
`endif
 
 
`ifdef PLL
`ifdef PLL
`ifndef SYNC_RST
`ifndef SYNC_RST
`define SYNC_RST
`define SYNC_RST
`endif
`endif
`endif
`endif
 
 
`ifdef SYNC_RST
`ifdef SYNC_RST
`ifndef GBUF
`ifndef GBUF
`define GBUF
`define GBUF
`endif
`endif
`endif
`endif
 
 
`ifdef WB_DPRAM
`ifdef WB_DPRAM
`ifndef WB_ADR_INC
`ifndef WB_ADR_INC
`define WB_ADR_INC
`define WB_ADR_INC
`endif
`endif
`ifndef DPRAM_BE_2R2W
`ifndef DPRAM_BE_2R2W
`define DPRAM_BE_2R2W
`define DPRAM_BE_2R2W
`endif
`endif
`endif
`endif
 
 
`ifdef WB3_ARBITER_TYPE1
`ifdef WB3_ARBITER_TYPE1
`ifndef SPR
`ifndef SPR
`define SPR
`define SPR
`endif
`endif
`ifndef MUX_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
`endif
`endif
 
 
`ifdef WB3AVALON_BRIDGE
`ifdef WB3AVALON_BRIDGE
`ifndef WB3WB3_BRIDGE
`ifndef WB3WB3_BRIDGE
`define WB3WB3_BRIDGE
`define WB3WB3_BRIDGE
`endif
`endif
`endif
`endif
 
 
`ifdef WB3WB3_BRIDGE
`ifdef WB3WB3_BRIDGE
`ifndef CNT_SHREG_CE_CLEAR
`ifndef CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`endif
`endif
`ifndef DFF
`ifndef DFF
`define DFF
`define DFF
`endif
`endif
`ifndef DFF_CE
`ifndef DFF_CE
`define DFF_CE
`define DFF_CE
`endif
`endif
`ifndef CNT_SHREG_CE_CLEAR
`ifndef CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`endif
`endif
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
`define FIFO_2R2W_ASYNC_SIMPLEX
`define FIFO_2R2W_ASYNC_SIMPLEX
`endif
`endif
`endif
`endif
 
 
 
 
`ifdef WB_AVALON_MEM_CACHE
`ifdef WB_AVALON_MEM_CACHE
`ifndef WB_SHADOW_RAM
`ifndef WB_SHADOW_RAM
`define WB_SHADOW_RAM
`define WB_SHADOW_RAM
`endif
`endif
`ifndef WB_CACHE
`ifndef WB_CACHE
`define WB_CACHE
`define WB_CACHE
`endif
`endif
`ifndef WB_AVALON_BRIDGE
`ifndef WB_AVALON_BRIDGE
`define WB_AVALON_BRIDGE
`define WB_AVALON_BRIDGE
`endif
`endif
`endif
`endif
 
 
`ifdef WB_CACHE
`ifdef WB_CACHE
`ifndef RAM
`ifndef RAM
`define RAM
`define RAM
`endif
`endif
`ifndef WB_ADR_INC
`ifndef WB_ADR_INC
`define WB_ADR_INC
`define WB_ADR_INC
`endif
`endif
`ifndef DPRAM_1R1W
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`define DPRAM_1R1W
`endif
`endif
`ifndef DPRAM_1R2W
`ifndef DPRAM_1R2W
`define DPRAM_1R2W
`define DPRAM_1R2W
`endif
`endif
`ifndef DPRAM_BE_2R2W
`ifndef DPRAM_BE_2R2W
`define DPRAM_BE_2R2W
`define DPRAM_BE_2R2W
`endif
`endif
`ifndef CDC
`ifndef CDC
`define CDC
`define CDC
`endif
`endif
`endif
`endif
 
 
`ifdef WB_SHADOW_RAM
`ifdef WB_SHADOW_RAM
`ifndef WB_RAM
`ifndef WB_RAM
`define WB_RAM
`define WB_RAM
`endif
`endif
`endif
`endif
 
 
`ifdef WB_RAM
`ifdef WB_RAM
`ifndef WB_ADR_INC
`ifndef WB_ADR_INC
`define WB_ADR_INC
`define WB_ADR_INC
`endif
`endif
`ifndef RAM_BE
`ifndef RAM_BE
`define RAM_BE
`define RAM_BE
`endif
`endif
`endif
`endif
 
 
`ifdef MULTS18X18
`ifdef MULTS18X18
`ifndef MULTS
`ifndef MULTS
`define MULTS
`define MULTS
`endif
`endif
`endif
`endif
 
 
`ifdef SHIFT_UNIT_32
`ifdef SHIFT_UNIT_32
`ifndef MULTS
`ifndef MULTS
`define MULTS
`define MULTS
`endif
`endif
`endif
`endif
 
 
`ifdef MUX2_ANDOR
`ifdef MUX2_ANDOR
`ifndef MUX_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
`endif
`endif
 
 
`ifdef MUX3_ANDOR
`ifdef MUX3_ANDOR
`ifndef MUX_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
`endif
`endif
 
 
`ifdef MUX4_ANDOR
`ifdef MUX4_ANDOR
`ifndef MUX_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
`endif
`endif
 
 
`ifdef MUX5_ANDOR
`ifdef MUX5_ANDOR
`ifndef MUX_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
`endif
`endif
 
 
`ifdef MUX6_ANDOR
`ifdef MUX6_ANDOR
`ifndef MUX_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
`endif
`endif
 
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifndef CNT_BIN_CE
`ifndef CNT_BIN_CE
`define CNT_BIN_CE
`define CNT_BIN_CE
`endif
`endif
`ifndef DPRAM_1R1W
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`define DPRAM_1R1W
`endif
`endif
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
`define CNT_BIN_CE_REW_Q_ZQ_L1
`define CNT_BIN_CE_REW_Q_ZQ_L1
`endif
`endif
`endif
`endif
 
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifndef CNT_LFSR_CE
`ifndef CNT_LFSR_CE
`define CNT_LFSR_CE
`define CNT_LFSR_CE
`endif
`endif
`ifndef DPRAM_2R2W
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`define DPRAM_2R2W
`endif
`endif
`ifndef CNT_BIN_CE_REW_ZQ_L1
`ifndef CNT_BIN_CE_REW_ZQ_L1
`define CNT_BIN_CE_REW_ZQ_L1
`define CNT_BIN_CE_REW_ZQ_L1
`endif
`endif
`endif
`endif
 
 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
`ifndef CNT_GRAY_CE_BIN
`ifndef CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`endif
`endif
`ifndef DPRAM_2R2W
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`define DPRAM_2R2W
`endif
`endif
`ifndef FIFO_CMP_ASYNC
`ifndef FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`endif
`endif
`endif
`endif
 
 
`ifdef FIFO_2R2W_ASYNC
`ifdef FIFO_2R2W_ASYNC
`ifndef FIFO_1R1W_ASYNC
`ifndef FIFO_1R1W_ASYNC
`define FIFO_1R1W_ASYNC
`define FIFO_1R1W_ASYNC
`endif
`endif
`endif
`endif
 
 
`ifdef FIFO_1R1W_ASYNC
`ifdef FIFO_1R1W_ASYNC
`ifndef CNT_GRAY_CE_BIN
`ifndef CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`endif
`endif
`ifndef DPRAM_1R1W
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`define DPRAM_1R1W
`endif
`endif
`ifndef FIFO_CMP_ASYNC
`ifndef FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`endif
`endif
`endif
`endif
 
 
`ifdef FIFO_CMP_ASYNC
`ifdef FIFO_CMP_ASYNC
`ifndef DFF_SR
`ifndef DFF_SR
`define DFF_SR
`define DFF_SR
`endif
`endif
`ifndef DFF
`ifndef DFF
`define DFF
`define DFF
`endif
`endif
`endif
`endif
 
 
`ifdef REG_FILE
`ifdef REG_FILE
`ifndef DPRAM_1R1W
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`define DPRAM_1R1W
`endif
`endif
`endif
`endif
 
 
`ifdef CDC
`ifdef CDC
`ifndef PULSE2TOGGLE
`ifndef PULSE2TOGGLE
`define PULSE2TOGGLE
`define PULSE2TOGGLE
`endif
`endif
`ifndef TOGGLE2PULSE
`ifndef TOGGLE2PULSE
`define TOGGLE2PULSE
`define TOGGLE2PULSE
`endif
`endif
`ifndef SYNCHRONIZER
`ifndef SYNCHRONIZER
`define SYNCHRONIZER
`define SYNCHRONIZER
`endif
`endif
`endif
`endif
 
 
// size to width
// size to width
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile library, clock and reset                          ////
////  Versatile library, clock and reset                          ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Logic related to clock and reset                            ////
////  Logic related to clock and reset                            ////
////                                                              ////
////                                                              ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add more different registers                             ////
////   - add more different registers                             ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
`ifdef ACTEL
`ifdef ACTEL
`ifdef GBUF
`ifdef GBUF
`timescale 1 ns/100 ps
`timescale 1 ns/100 ps
// Global buffer
// Global buffer
// usage:
// usage:
// use to enable global buffers for high fan out signals such as clock and reset
// use to enable global buffers for high fan out signals such as clock and reset
// Version: 8.4 8.4.0.33
// Version: 8.4 8.4.0.33
module gbuf(GL,CLK);
module gbuf(GL,CLK);
output GL;
output GL;
input  CLK;
input  CLK;
 
 
    wire GND;
    wire GND;
 
 
    GND GND_1_net(.Y(GND));
    GND GND_1_net(.Y(GND));
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
 
 
endmodule
endmodule
`timescale 1 ns/1 ns
`timescale 1 ns/1 ns
`define MODULE gbuf
`define MODULE gbuf
module `BASE`MODULE ( i, o);
module `BASE`MODULE ( i, o);
`undef MODULE
`undef MODULE
input i;
input i;
output o;
output o;
`ifdef SIM_GBUF
`ifdef SIM_GBUF
assign o=i;
assign o=i;
`else
`else
gbuf gbuf_i0 ( .CLK(i), .GL(o));
gbuf gbuf_i0 ( .CLK(i), .GL(o));
`endif
`endif
endmodule
endmodule
`endif
`endif
 
 
`else
`else
 
 
`ifdef ALTERA
`ifdef ALTERA
`ifdef GBUF
`ifdef GBUF
//altera
//altera
`define MODULE gbuf
`define MODULE gbuf
module `BASE`MODULE ( i, o);
module `BASE`MODULE ( i, o);
`undef MODULE
`undef MODULE
input i;
input i;
output o;
output o;
assign o = i;
assign o = i;
endmodule
endmodule
`endif
`endif
 
 
`else
`else
 
 
`ifdef GBUF
`ifdef GBUF
`timescale 1 ns/100 ps
`timescale 1 ns/100 ps
`define MODULE
`define MODULE
module `BASE`MODULE ( i, o);
module `BASE`MODULE ( i, o);
`undef MODULE
`undef MODULE
input i;
input i;
output o;
output o;
assign o = i;
assign o = i;
endmodule
endmodule
`endif
`endif
`endif // ALTERA
`endif // ALTERA
`endif //ACTEL
`endif //ACTEL
 
 
`ifdef SYNC_RST
`ifdef SYNC_RST
// sync reset
// sync reset
// input active lo async reset, normally from external reset generator and/or switch
// input active lo async reset, normally from external reset generator and/or switch
// output active high global reset sync with two DFFs 
// output active high global reset sync with two DFFs 
`timescale 1 ns/100 ps
`timescale 1 ns/100 ps
`define MODULE sync_rst
`define MODULE sync_rst
module `BASE`MODULE ( rst_n_i, rst_o, clk);
module `BASE`MODULE ( rst_n_i, rst_o, clk);
`undef MODULE
`undef MODULE
input rst_n_i, clk;
input rst_n_i, clk;
output rst_o;
output rst_o;
reg [1:0] tmp;
reg [1:0] tmp;
always @ (posedge clk or negedge rst_n_i)
always @ (posedge clk or negedge rst_n_i)
if (!rst_n_i)
if (!rst_n_i)
        tmp <= 2'b11;
        tmp <= 2'b11;
else
else
        tmp <= {1'b0,tmp[1]};
        tmp <= {1'b0,tmp[1]};
`define MODULE gbuf
`define MODULE gbuf
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
`undef MODULE
`undef MODULE
endmodule
endmodule
`endif
`endif
 
 
`ifdef PLL
`ifdef PLL
// vl_pll
// vl_pll
`ifdef ACTEL
`ifdef ACTEL
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
`timescale 1 ps/1 ps
`define MODULE pll
`define MODULE pll
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
`undef MODULE
`undef MODULE
parameter index = 0;
parameter index = 0;
parameter number_of_clk = 1;
parameter number_of_clk = 1;
parameter period_time_0 = 20000;
parameter period_time_0 = 20000;
parameter period_time_1 = 20000;
parameter period_time_1 = 20000;
parameter period_time_2 = 20000;
parameter period_time_2 = 20000;
parameter lock_delay = 2000000;
parameter lock_delay = 2000000;
input clk_i, rst_n_i;
input clk_i, rst_n_i;
output lock;
output lock;
output reg [0:number_of_clk-1] clk_o;
output reg [0:number_of_clk-1] clk_o;
output [0:number_of_clk-1] rst_o;
output [0:number_of_clk-1] rst_o;
 
 
`ifdef SIM_PLL
`ifdef SIM_PLL
 
 
always
always
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
 
 
generate if (number_of_clk > 1)
generate if (number_of_clk > 1)
always
always
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
endgenerate
endgenerate
 
 
generate if (number_of_clk > 2)
generate if (number_of_clk > 2)
always
always
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
endgenerate
endgenerate
 
 
genvar i;
genvar i;
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
end
end
endgenerate
endgenerate
 
 
assign #lock_delay lock = rst_n_i;
assign #lock_delay lock = rst_n_i;
 
 
endmodule
endmodule
`else
`else
generate if (number_of_clk==1 & index==0) begin
generate if (number_of_clk==1 & index==0) begin
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
end
end
endgenerate // index==0
endgenerate // index==0
generate if (number_of_clk==1 & index==1) begin
generate if (number_of_clk==1 & index==1) begin
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
end
end
endgenerate // index==1
endgenerate // index==1
generate if (number_of_clk==1 & index==2) begin
generate if (number_of_clk==1 & index==2) begin
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
end
end
endgenerate // index==2
endgenerate // index==2
generate if (number_of_clk==1 & index==3) begin
generate if (number_of_clk==1 & index==3) begin
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
end
end
endgenerate // index==0
endgenerate // index==0
 
 
generate if (number_of_clk==2 & index==0) begin
generate if (number_of_clk==2 & index==0) begin
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
end
end
endgenerate // index==0
endgenerate // index==0
generate if (number_of_clk==2 & index==1) begin
generate if (number_of_clk==2 & index==1) begin
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
end
end
endgenerate // index==1
endgenerate // index==1
generate if (number_of_clk==2 & index==2) begin
generate if (number_of_clk==2 & index==2) begin
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
end
end
endgenerate // index==2
endgenerate // index==2
generate if (number_of_clk==2 & index==3) begin
generate if (number_of_clk==2 & index==3) begin
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
end
end
endgenerate // index==0
endgenerate // index==0
 
 
generate if (number_of_clk==3 & index==0) begin
generate if (number_of_clk==3 & index==0) begin
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
end
end
endgenerate // index==0
endgenerate // index==0
generate if (number_of_clk==3 & index==1) begin
generate if (number_of_clk==3 & index==1) begin
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
end
end
endgenerate // index==1
endgenerate // index==1
generate if (number_of_clk==3 & index==2) begin
generate if (number_of_clk==3 & index==2) begin
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
end
end
endgenerate // index==2
endgenerate // index==2
generate if (number_of_clk==3 & index==3) begin
generate if (number_of_clk==3 & index==3) begin
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
end
end
endgenerate // index==0
endgenerate // index==0
 
 
genvar i;
genvar i;
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
`define MODULE sync_rst
`define MODULE sync_rst
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
`undef MODULE
`undef MODULE
end
end
endgenerate
endgenerate
endmodule
endmodule
`endif
`endif
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
 
 
`else
`else
 
 
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`ifdef ALTERA
`ifdef ALTERA
 
 
`timescale 1 ps/1 ps
`timescale 1 ps/1 ps
`define MODULE pll
`define MODULE pll
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
`undef MODULE
`undef MODULE
parameter index = 0;
parameter index = 0;
parameter number_of_clk = 1;
parameter number_of_clk = 1;
parameter period_time_0 = 20000;
parameter period_time_0 = 20000;
parameter period_time_1 = 20000;
parameter period_time_1 = 20000;
parameter period_time_2 = 20000;
parameter period_time_2 = 20000;
parameter period_time_3 = 20000;
parameter period_time_3 = 20000;
parameter period_time_4 = 20000;
parameter period_time_4 = 20000;
parameter lock_delay = 2000000;
parameter lock_delay = 2000000;
input clk_i, rst_n_i;
input clk_i, rst_n_i;
output lock;
output lock;
output reg [0:number_of_clk-1] clk_o;
output reg [0:number_of_clk-1] clk_o;
output [0:number_of_clk-1] rst_o;
output [0:number_of_clk-1] rst_o;
 
 
`ifdef SIM_PLL
`ifdef SIM_PLL
 
 
always
always
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
 
 
generate if (number_of_clk > 1)
generate if (number_of_clk > 1)
always
always
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
endgenerate
endgenerate
 
 
generate if (number_of_clk > 2)
generate if (number_of_clk > 2)
always
always
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
endgenerate
endgenerate
 
 
generate if (number_of_clk > 3)
generate if (number_of_clk > 3)
always
always
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
endgenerate
endgenerate
 
 
generate if (number_of_clk > 4)
generate if (number_of_clk > 4)
always
always
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
endgenerate
endgenerate
 
 
genvar i;
genvar i;
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
end
end
endgenerate
endgenerate
 
 
//assign #lock_delay lock = rst_n_i;
//assign #lock_delay lock = rst_n_i;
assign lock = rst_n_i;
assign lock = rst_n_i;
 
 
endmodule
endmodule
`else
`else
 
 
`ifdef VL_PLL0
`ifdef VL_PLL0
`ifdef VL_PLL0_CLK1
`ifdef VL_PLL0_CLK1
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
`endif
`endif
`ifdef VL_PLL0_CLK2
`ifdef VL_PLL0_CLK2
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
`endif
`endif
`ifdef VL_PLL0_CLK3
`ifdef VL_PLL0_CLK3
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
`endif
`endif
`ifdef VL_PLL0_CLK4
`ifdef VL_PLL0_CLK4
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
`endif
`endif
`ifdef VL_PLL0_CLK5
`ifdef VL_PLL0_CLK5
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
`endif
`endif
`endif
`endif
 
 
`ifdef VL_PLL1
`ifdef VL_PLL1
`ifdef VL_PLL1_CLK1
`ifdef VL_PLL1_CLK1
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
`endif
`endif
`ifdef VL_PLL1_CLK2
`ifdef VL_PLL1_CLK2
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
`endif
`endif
`ifdef VL_PLL1_CLK3
`ifdef VL_PLL1_CLK3
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
`endif
`endif
`ifdef VL_PLL1_CLK4
`ifdef VL_PLL1_CLK4
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
`endif
`endif
`ifdef VL_PLL1_CLK5
`ifdef VL_PLL1_CLK5
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
`endif
`endif
`endif
`endif
 
 
`ifdef VL_PLL2
`ifdef VL_PLL2
`ifdef VL_PLL2_CLK1
`ifdef VL_PLL2_CLK1
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
`endif
`endif
`ifdef VL_PLL2_CLK2
`ifdef VL_PLL2_CLK2
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
`endif
`endif
`ifdef VL_PLL2_CLK3
`ifdef VL_PLL2_CLK3
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
`endif
`endif
`ifdef VL_PLL2_CLK4
`ifdef VL_PLL2_CLK4
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
`endif
`endif
`ifdef VL_PLL2_CLK5
`ifdef VL_PLL2_CLK5
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
`endif
`endif
`endif
`endif
 
 
`ifdef VL_PLL3
`ifdef VL_PLL3
`ifdef VL_PLL3_CLK1
`ifdef VL_PLL3_CLK1
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
`endif
`endif
`ifdef VL_PLL3_CLK2
`ifdef VL_PLL3_CLK2
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
`endif
`endif
`ifdef VL_PLL3_CLK3
`ifdef VL_PLL3_CLK3
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
`endif
`endif
`ifdef VL_PLL3_CLK4
`ifdef VL_PLL3_CLK4
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
`endif
`endif
`ifdef VL_PLL3_CLK5
`ifdef VL_PLL3_CLK5
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
`endif
`endif
`endif
`endif
 
 
genvar i;
genvar i;
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
`define MODULE sync_rst
`define MODULE sync_rst
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
`undef MODULE
`undef MODULE
end
end
endgenerate
endgenerate
endmodule
endmodule
`endif
`endif
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
 
 
`else
`else
 
 
// generic PLL
// generic PLL
`timescale 1 ps/1 ps
`timescale 1 ps/1 ps
`define MODULE pll
`define MODULE pll
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
`undef MODULE
`undef MODULE
parameter index = 0;
parameter index = 0;
parameter number_of_clk = 1;
parameter number_of_clk = 1;
parameter period_time_0 = 20000;
parameter period_time_0 = 20000;
parameter period_time_1 = 20000;
parameter period_time_1 = 20000;
parameter period_time_2 = 20000;
parameter period_time_2 = 20000;
parameter lock_delay = 2000;
parameter lock_delay = 2000;
input clk_i, rst_n_i;
input clk_i, rst_n_i;
output lock;
output lock;
output reg [0:number_of_clk-1] clk_o;
output reg [0:number_of_clk-1] clk_o;
output [0:number_of_clk-1] rst_o;
output [0:number_of_clk-1] rst_o;
 
 
always
always
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
 
 
generate if (number_of_clk > 1)
generate if (number_of_clk > 1)
always
always
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
endgenerate
endgenerate
 
 
generate if (number_of_clk > 2)
generate if (number_of_clk > 2)
always
always
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
endgenerate
endgenerate
 
 
genvar i;
genvar i;
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
`define MODULE sync_rst
`define MODULE sync_rst
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
`undef MODULE
`undef MODULE
end
end
endgenerate
endgenerate
 
 
assign #lock_delay lock = rst_n_i;
assign #lock_delay lock = rst_n_i;
 
 
endmodule
endmodule
 
 
`endif //altera
`endif //altera
`endif //actel
`endif //actel
`undef MODULE
`undef MODULE
`endif//////////////////////////////////////////////////////////////////////
`endif//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile library, registers                                ////
////  Versatile library, registers                                ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Different type of registers                                 ////
////  Different type of registers                                 ////
////                                                              ////
////                                                              ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add more different registers                             ////
////   - add more different registers                             ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
`ifdef DFF
`ifdef DFF
`define MODULE dff
`define MODULE dff
module `BASE`MODULE ( d, q, clk, rst);
module `BASE`MODULE ( d, q, clk, rst);
`undef MODULE
`undef MODULE
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = 0;
 
 
        input [width-1:0] d;
        input [width-1:0] d;
        input clk, rst;
        input clk, rst;
        output reg [width-1:0] q;
        output reg [width-1:0] q;
 
 
        always @ (posedge clk or posedge rst)
        always @ (posedge clk or posedge rst)
        if (rst)
        if (rst)
                q <= reset_value;
                q <= reset_value;
        else
        else
                q <= d;
                q <= d;
 
 
endmodule
endmodule
`endif
`endif
 
 
`ifdef DFF_ARRAY
`ifdef DFF_ARRAY
`define MODULE dff_array
`define MODULE dff_array
module `BASE`MODULE ( d, q, clk, rst);
module `BASE`MODULE ( d, q, clk, rst);
`undef MODULE
`undef MODULE
 
 
        parameter width = 1;
        parameter width = 1;
        parameter depth = 2;
        parameter depth = 2;
        parameter reset_value = 1'b0;
        parameter reset_value = 1'b0;
 
 
        input [width-1:0] d;
        input [width-1:0] d;
        input clk, rst;
        input clk, rst;
        output [width-1:0] q;
        output [width-1:0] q;
        reg  [0:depth-1] q_tmp [width-1:0];
        reg  [0:depth-1] q_tmp [width-1:0];
        integer i;
        integer i;
        always @ (posedge clk or posedge rst)
        always @ (posedge clk or posedge rst)
        if (rst) begin
        if (rst) begin
            for (i=0;i<depth;i=i+1)
            for (i=0;i<depth;i=i+1)
                q_tmp[i] <= {width{reset_value}};
                q_tmp[i] <= {width{reset_value}};
        end else begin
        end else begin
            q_tmp[0] <= d;
            q_tmp[0] <= d;
            for (i=1;i<depth;i=i+1)
            for (i=1;i<depth;i=i+1)
                q_tmp[i] <= q_tmp[i-1];
                q_tmp[i] <= q_tmp[i-1];
        end
        end
 
 
    assign q = q_tmp[depth-1];
    assign q = q_tmp[depth-1];
 
 
endmodule
endmodule
`endif
`endif
 
 
`ifdef DFF_CE
`ifdef DFF_CE
`define MODULE dff_ce
`define MODULE dff_ce
module `BASE`MODULE ( d, ce, q, clk, rst);
module `BASE`MODULE ( d, ce, q, clk, rst);
`undef MODULE
`undef MODULE
 
 
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = 0;
 
 
        input [width-1:0] d;
        input [width-1:0] d;
        input ce, clk, rst;
        input ce, clk, rst;
        output reg [width-1:0] q;
        output reg [width-1:0] q;
 
 
        always @ (posedge clk or posedge rst)
        always @ (posedge clk or posedge rst)
        if (rst)
        if (rst)
                q <= reset_value;
                q <= reset_value;
        else
        else
                if (ce)
                if (ce)
                        q <= d;
                        q <= d;
 
 
endmodule
endmodule
`endif
`endif
 
 
`ifdef DFF_CE_CLEAR
`ifdef DFF_CE_CLEAR
`define MODULE dff_ce_clear
`define MODULE dff_ce_clear
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
`undef MODULE
`undef MODULE
 
 
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = 0;
 
 
        input [width-1:0] d;
        input [width-1:0] d;
        input ce, clear, clk, rst;
        input ce, clear, clk, rst;
        output reg [width-1:0] q;
        output reg [width-1:0] q;
 
 
        always @ (posedge clk or posedge rst)
        always @ (posedge clk or posedge rst)
        if (rst)
        if (rst)
            q <= reset_value;
            q <= reset_value;
        else
        else
            if (ce)
            if (ce)
                if (clear)
                if (clear)
                    q <= {width{1'b0}};
                    q <= {width{1'b0}};
                else
                else
                    q <= d;
                    q <= d;
 
 
endmodule
endmodule
`endif
`endif
 
 
`ifdef DF_CE_SET
`ifdef DF_CE_SET
`define MODULE dff_ce_set
`define MODULE dff_ce_set
module `BASE`MODULE ( d, ce, set, q, clk, rst);
module `BASE`MODULE ( d, ce, set, q, clk, rst);
`undef MODULE
`undef MODULE
 
 
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = 0;
 
 
        input [width-1:0] d;
        input [width-1:0] d;
        input ce, set, clk, rst;
        input ce, set, clk, rst;
        output reg [width-1:0] q;
        output reg [width-1:0] q;
 
 
        always @ (posedge clk or posedge rst)
        always @ (posedge clk or posedge rst)
        if (rst)
        if (rst)
            q <= reset_value;
            q <= reset_value;
        else
        else
            if (ce)
            if (ce)
                if (set)
                if (set)
                    q <= {width{1'b1}};
                    q <= {width{1'b1}};
                else
                else
                    q <= d;
                    q <= d;
 
 
endmodule
endmodule
`endif
`endif
 
 
`ifdef SPR
`ifdef SPR
`define MODULE spr
`define MODULE spr
module `BASE`MODULE ( sp, r, q, clk, rst);
module `BASE`MODULE ( sp, r, q, clk, rst);
`undef MODULE
`undef MODULE
 
 
        //parameter width = 1;
        //parameter width = 1;
        parameter reset_value = 1'b0;
        parameter reset_value = 1'b0;
 
 
        input sp, r;
        input sp, r;
        output reg q;
        output reg q;
        input clk, rst;
        input clk, rst;
 
 
        always @ (posedge clk or posedge rst)
        always @ (posedge clk or posedge rst)
        if (rst)
        if (rst)
            q <= reset_value;
            q <= reset_value;
        else
        else
            if (sp)
            if (sp)
                q <= 1'b1;
                q <= 1'b1;
            else if (r)
            else if (r)
                q <= 1'b0;
                q <= 1'b0;
 
 
endmodule
endmodule
`endif
`endif
 
 
`ifdef SRP
`ifdef SRP
`define MODULE srp
`define MODULE srp
module `BASE`MODULE ( s, rp, q, clk, rst);
module `BASE`MODULE ( s, rp, q, clk, rst);
`undef MODULE
`undef MODULE
 
 
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = 0;
 
 
        input s, rp;
        input s, rp;
        output reg q;
        output reg q;
        input clk, rst;
        input clk, rst;
 
 
        always @ (posedge clk or posedge rst)
        always @ (posedge clk or posedge rst)
        if (rst)
        if (rst)
            q <= reset_value;
            q <= reset_value;
        else
        else
            if (rp)
            if (rp)
                q <= 1'b0;
                q <= 1'b0;
            else if (s)
            else if (s)
                q <= 1'b1;
                q <= 1'b1;
 
 
endmodule
endmodule
`endif
`endif
 
 
`ifdef ALTERA
`ifdef ALTERA
 
 
`ifdef DFF_SR
`ifdef DFF_SR
// megafunction wizard: %LPM_FF%
// megafunction wizard: %LPM_FF%
// GENERATION: STANDARD
// GENERATION: STANDARD
// VERSION: WM1.0
// VERSION: WM1.0
// MODULE: lpm_ff 
// MODULE: lpm_ff 
 
 
// ============================================================
// ============================================================
// File Name: dff_sr.v
// File Name: dff_sr.v
// Megafunction Name(s):
// Megafunction Name(s):
//                      lpm_ff
//                      lpm_ff
//
//
// Simulation Library Files(s):
// Simulation Library Files(s):
//                      lpm
//                      lpm
// ============================================================
// ============================================================
// ************************************************************
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
//
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
// ************************************************************
// ************************************************************
 
 
 
 
//Copyright (C) 1991-2010 Altera Corporation
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions 
//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files from any of the foregoing 
//functions, and any output files from any of the foregoing 
//(including device programming or simulation files), and any 
//(including device programming or simulation files), and any 
//associated documentation or information are expressly subject 
//associated documentation or information are expressly subject 
//to the terms and conditions of the Altera Program License 
//to the terms and conditions of the Altera Program License 
//Subscription Agreement, Altera MegaCore Function License 
//Subscription Agreement, Altera MegaCore Function License 
//Agreement, or other applicable license agreement, including, 
//Agreement, or other applicable license agreement, including, 
//without limitation, that your use is for the sole purpose of 
//without limitation, that your use is for the sole purpose of 
//programming logic devices manufactured by Altera and sold by 
//programming logic devices manufactured by Altera and sold by 
//Altera or its authorized distributors.  Please refer to the 
//Altera or its authorized distributors.  Please refer to the 
//applicable agreement for further details.
//applicable agreement for further details.
 
 
 
 
// synopsys translate_off
// synopsys translate_off
`timescale 1 ps / 1 ps
`timescale 1 ps / 1 ps
// synopsys translate_on
// synopsys translate_on
`define MODULE dff_sr
`define MODULE dff_sr
module `BASE`MODULE (
module `BASE`MODULE (
`undef MODULE
`undef MODULE
 
 
        aclr,
        aclr,
        aset,
        aset,
        clock,
        clock,
        data,
        data,
        q);
        q);
 
 
        input     aclr;
        input     aclr;
        input     aset;
        input     aset;
        input     clock;
        input     clock;
        input     data;
        input     data;
        output    q;
        output    q;
 
 
        wire [0:0] sub_wire0;
        wire [0:0] sub_wire0;
        wire [0:0] sub_wire1 = sub_wire0[0:0];
        wire [0:0] sub_wire1 = sub_wire0[0:0];
        wire  q = sub_wire1;
        wire  q = sub_wire1;
        wire  sub_wire2 = data;
        wire  sub_wire2 = data;
        wire  sub_wire3 = sub_wire2;
        wire  sub_wire3 = sub_wire2;
 
 
        lpm_ff  lpm_ff_component (
        lpm_ff  lpm_ff_component (
                                .aclr (aclr),
                                .aclr (aclr),
                                .clock (clock),
                                .clock (clock),
                                .data (sub_wire3),
                                .data (sub_wire3),
                                .aset (aset),
                                .aset (aset),
                                .q (sub_wire0)
                                .q (sub_wire0)
                                // synopsys translate_off
                                // synopsys translate_off
                                ,
                                ,
                                .aload (),
                                .aload (),
                                .enable (),
                                .enable (),
                                .sclr (),
                                .sclr (),
                                .sload (),
                                .sload (),
                                .sset ()
                                .sset ()
                                // synopsys translate_on
                                // synopsys translate_on
                                );
                                );
        defparam
        defparam
                lpm_ff_component.lpm_fftype = "DFF",
                lpm_ff_component.lpm_fftype = "DFF",
                lpm_ff_component.lpm_type = "LPM_FF",
                lpm_ff_component.lpm_type = "LPM_FF",
                lpm_ff_component.lpm_width = 1;
                lpm_ff_component.lpm_width = 1;
 
 
 
 
endmodule
endmodule
 
 
// ============================================================
// ============================================================
// CNX file retrieval info
// CNX file retrieval info
// ============================================================
// ============================================================
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
// Retrieval info: PRIVATE: ASET NUMERIC "1"
// Retrieval info: PRIVATE: ASET NUMERIC "1"
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
// Retrieval info: PRIVATE: DFF NUMERIC "1"
// Retrieval info: PRIVATE: DFF NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: SSET NUMERIC "0"
// Retrieval info: PRIVATE: SSET NUMERIC "0"
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
// Retrieval info: PRIVATE: nBit NUMERIC "1"
// Retrieval info: PRIVATE: nBit NUMERIC "1"
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
// Retrieval info: LIB_FILE: lpm
`endif
`endif
 
 
`else
`else
 
 
`ifdef DFF_SR
`ifdef DFF_SR
`define MODULE dff_sr
`define MODULE dff_sr
module `BASE`MODULE ( aclr, aset, clock, data, q);
module `BASE`MODULE ( aclr, aset, clock, data, q);
`undef MODULE
`undef MODULE
 
 
    input         aclr;
    input         aclr;
    input         aset;
    input         aset;
    input         clock;
    input         clock;
    input         data;
    input         data;
    output reg    q;
    output reg    q;
 
 
   always @ (posedge clock or posedge aclr or posedge aset)
   always @ (posedge clock or posedge aclr or posedge aset)
     if (aclr)
     if (aclr)
       q <= 1'b0;
       q <= 1'b0;
     else if (aset)
     else if (aset)
       q <= 1'b1;
       q <= 1'b1;
     else
     else
       q <= data;
       q <= data;
 
 
endmodule
endmodule
`endif
`endif
 
 
`endif
`endif
 
 
// LATCH
// LATCH
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
`ifdef ALTERA
`ifdef ALTERA
 
 
`ifdef LATCH
`ifdef LATCH
`define MODULE latch
`define MODULE latch
module `BASE`MODULE ( d, le, q, clk);
module `BASE`MODULE ( d, le, q, clk);
`undef MODULE
`undef MODULE
input d, le;
input d, le;
output q;
output q;
input clk;
input clk;
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
endmodule
endmodule
`endif
`endif
 
 
`else
`else
 
 
`ifdef LATCH
`ifdef LATCH
`define MODULE latch
`define MODULE latch
module `BASE`MODULE ( d, le, q, clk);
module `BASE`MODULE ( d, le, q, clk);
`undef MODULE
`undef MODULE
input d, le;
input d, le;
input clk;
input clk;
always @ (le or d)
always @ (le or d)
if (le)
if (le)
    d <= q;
    d <= q;
endmodule
endmodule
`endif
`endif
 
 
`endif
`endif
 
 
`ifdef SHREG
`ifdef SHREG
`define MODULE shreg
`define MODULE shreg
module `BASE`MODULE ( d, q, clk, rst);
module `BASE`MODULE ( d, q, clk, rst);
`undef MODULE
`undef MODULE
 
 
parameter depth = 10;
parameter depth = 10;
input d;
input d;
output q;
output q;
input clk, rst;
input clk, rst;
 
 
reg [1:depth] dffs;
reg [1:depth] dffs;
 
 
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
if (rst)
if (rst)
    dffs <= {depth{1'b0}};
    dffs <= {depth{1'b0}};
else
else
    dffs <= {d,dffs[1:depth-1]};
    dffs <= {d,dffs[1:depth-1]};
assign q = dffs[depth];
assign q = dffs[depth];
endmodule
endmodule
`endif
`endif
 
 
`ifdef SHREG_CE
`ifdef SHREG_CE
`define MODULE shreg_ce
`define MODULE shreg_ce
module `BASE`MODULE ( d, ce, q, clk, rst);
module `BASE`MODULE ( d, ce, q, clk, rst);
`undef MODULE
`undef MODULE
parameter depth = 10;
parameter depth = 10;
input d, ce;
input d, ce;
output q;
output q;
input clk, rst;
input clk, rst;
 
 
reg [1:depth] dffs;
reg [1:depth] dffs;
 
 
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
if (rst)
if (rst)
    dffs <= {depth{1'b0}};
    dffs <= {depth{1'b0}};
else
else
    if (ce)
    if (ce)
        dffs <= {d,dffs[1:depth-1]};
        dffs <= {d,dffs[1:depth-1]};
assign q = dffs[depth];
assign q = dffs[depth];
endmodule
endmodule
`endif
`endif
 
 
`ifdef DELAY
`ifdef DELAY
`define MODULE delay
`define MODULE delay
module `BASE`MODULE ( d, q, clk, rst);
module `BASE`MODULE ( d, q, clk, rst);
`undef MODULE
`undef MODULE
parameter depth = 10;
parameter depth = 10;
input d;
input d;
output q;
output q;
input clk, rst;
input clk, rst;
 
 
reg [1:depth] dffs;
reg [1:depth] dffs;
 
 
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
if (rst)
if (rst)
    dffs <= {depth{1'b0}};
    dffs <= {depth{1'b0}};
else
else
    dffs <= {d,dffs[1:depth-1]};
    dffs <= {d,dffs[1:depth-1]};
assign q = dffs[depth];
assign q = dffs[depth];
endmodule
endmodule
`endif
`endif
 
 
`ifdef DELAY_EMPTYFLAG
`ifdef DELAY_EMPTYFLAG
`define MODULE delay_emptyflag
`define MODULE delay_emptyflag
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
`undef MODULE
`undef MODULE
parameter depth = 10;
parameter depth = 10;
input d;
input d;
output q, emptyflag;
output q, emptyflag;
input clk, rst;
input clk, rst;
 
 
reg [1:depth] dffs;
reg [1:depth] dffs;
 
 
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
if (rst)
if (rst)
    dffs <= {depth{1'b0}};
    dffs <= {depth{1'b0}};
else
else
    dffs <= {d,dffs[1:depth-1]};
    dffs <= {d,dffs[1:depth-1]};
assign q = dffs[depth];
assign q = dffs[depth];
assign emptyflag = !(|dffs);
assign emptyflag = !(|dffs);
endmodule
endmodule
`endif
`endif
 
 
`ifdef PULSE2TOGGLE
`ifdef PULSE2TOGGLE
`define MODULE pulse2toggle
`define MODULE pulse2toggle
module `BASE`MODULE ( pl, q, clk, rst);
module `BASE`MODULE ( pl, q, clk, rst);
`undef MODULE
`undef MODULE
input pl;
input pl;
output reg q;
output reg q;
input clk, rst;
input clk, rst;
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
if (rst)
if (rst)
    q <= 1'b0;
    q <= 1'b0;
else
else
    q <= pl ^ q;
    q <= pl ^ q;
endmodule
endmodule
`endif
`endif
 
 
`ifdef TOGGLE2PULSE
`ifdef TOGGLE2PULSE
`define MODULE toggle2pulse
`define MODULE toggle2pulse
module `BASE`MODULE (d, pl, clk, rst);
module `BASE`MODULE (d, pl, clk, rst);
`undef MODULE
`undef MODULE
input d;
input d;
output pl;
output pl;
input clk, rst;
input clk, rst;
reg dff;
reg dff;
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
if (rst)
if (rst)
    dff <= 1'b0;
    dff <= 1'b0;
else
else
    dff <= d;
    dff <= d;
assign pl = d ^ dff;
assign pl = d ^ dff;
endmodule
endmodule
`endif
`endif
 
 
`ifdef SYNCHRONIZER
`ifdef SYNCHRONIZER
`define MODULE synchronizer
`define MODULE synchronizer
module `BASE`MODULE (d, q, clk, rst);
module `BASE`MODULE (d, q, clk, rst);
`undef MODULE
`undef MODULE
input d;
input d;
output reg q;
output reg q;
input clk, rst;
input clk, rst;
reg dff;
reg dff;
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
if (rst)
if (rst)
    {q,dff} <= 2'b00;
    {q,dff} <= 2'b00;
else
else
    {q,dff} <= {dff,d};
    {q,dff} <= {dff,d};
endmodule
endmodule
`endif
`endif
 
 
`ifdef CDC
`ifdef CDC
`define MODULE cdc
`define MODULE cdc
module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
`undef MODULE
`undef MODULE
input start_pl;
input start_pl;
output take_it_pl;
output take_it_pl;
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
output got_it_pl;
output got_it_pl;
input clk_src, rst_src;
input clk_src, rst_src;
input clk_dst, rst_dst;
input clk_dst, rst_dst;
wire take_it_tg, take_it_tg_sync;
wire take_it_tg, take_it_tg_sync;
wire got_it_tg, got_it_tg_sync;
wire got_it_tg, got_it_tg_sync;
// src -> dst
// src -> dst
`define MODULE pulse2toggle
`define MODULE pulse2toggle
`BASE`MODULE p2t0 (
`BASE`MODULE p2t0 (
`undef MODULE
`undef MODULE
    .pl(start_pl),
    .pl(start_pl),
    .q(take_it_tg),
    .q(take_it_tg),
    .clk(clk_src),
    .clk(clk_src),
    .rst(rst_src));
    .rst(rst_src));
 
 
`define MODULE synchronizer
`define MODULE synchronizer
`BASE`MODULE sync0 (
`BASE`MODULE sync0 (
`undef MODULE
`undef MODULE
    .d(take_it_tg),
    .d(take_it_tg),
    .q(take_it_tg_sync),
    .q(take_it_tg_sync),
    .clk(clk_dst),
    .clk(clk_dst),
    .rst(rst_dst));
    .rst(rst_dst));
 
 
`define MODULE toggle2pulse
`define MODULE toggle2pulse
`BASE`MODULE t2p0 (
`BASE`MODULE t2p0 (
`undef MODULE
`undef MODULE
    .d(take_it_tg_sync),
    .d(take_it_tg_sync),
    .pl(take_it_pl),
    .pl(take_it_pl),
    .clk(clk_dst),
    .clk(clk_dst),
    .rst(rst_dst));
    .rst(rst_dst));
 
 
// dst -> src
// dst -> src
`define MODULE pulse2toggle
`define MODULE pulse2toggle
`BASE`MODULE p2t1 (
`BASE`MODULE p2t1 (
`undef MODULE
`undef MODULE
    .pl(take_it_grant_pl),
    .pl(take_it_grant_pl),
    .q(got_it_tg),
    .q(got_it_tg),
    .clk(clk_dst),
    .clk(clk_dst),
    .rst(rst_dst));
    .rst(rst_dst));
 
 
`define MODULE synchronizer
`define MODULE synchronizer
`BASE`MODULE sync1 (
`BASE`MODULE sync1 (
`undef MODULE
`undef MODULE
    .d(got_it_tg),
    .d(got_it_tg),
    .q(got_it_tg_sync),
    .q(got_it_tg_sync),
    .clk(clk_src),
    .clk(clk_src),
    .rst(rst_src));
    .rst(rst_src));
 
 
`define MODULE toggle2pulse
`define MODULE toggle2pulse
`BASE`MODULE t2p1 (
`BASE`MODULE t2p1 (
`undef MODULE
`undef MODULE
    .d(got_it_tg_sync),
    .d(got_it_tg_sync),
    .pl(got_it_pl),
    .pl(got_it_pl),
    .clk(clk_src),
    .clk(clk_src),
    .rst(rst_src));
    .rst(rst_src));
 
 
endmodule
endmodule
`endif
`endif
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Logic functions                                             ////
////  Logic functions                                             ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Logic functions such as multiplexers                        ////
////  Logic functions such as multiplexers                        ////
////                                                              ////
////                                                              ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   -                                                          ////
////   -                                                          ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
`ifdef MUX_ANDOR
`ifdef MUX_ANDOR
`define MODULE mux_andor
`define MODULE mux_andor
module `BASE`MODULE ( a, sel, dout);
module `BASE`MODULE ( a, sel, dout);
`undef MODULE
`undef MODULE
 
 
parameter width = 32;
parameter width = 32;
parameter nr_of_ports = 4;
parameter nr_of_ports = 4;
 
 
input [nr_of_ports*width-1:0] a;
input [nr_of_ports*width-1:0] a;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
output reg [width-1:0] dout;
 
 
integer i,j;
integer i,j;
 
 
always @ (a, sel)
always @ (a, sel)
begin
begin
    dout = a[width-1:0] & {width{sel[0]}};
    dout = a[width-1:0] & {width{sel[0]}};
    for (i=1;i<nr_of_ports;i=i+1)
    for (i=1;i<nr_of_ports;i=i+1)
        for (j=0;j<width;j=j+1)
        for (j=0;j<width;j=j+1)
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
end
end
 
 
endmodule
endmodule
`endif
`endif
 
 
`ifdef MUX2_ANDOR
`ifdef MUX2_ANDOR
`define MODULE mux2_andor
`define MODULE mux2_andor
module `BASE`MODULE ( a1, a0, sel, dout);
module `BASE`MODULE ( a1, a0, sel, dout);
`undef MODULE
`undef MODULE
 
 
parameter width = 32;
parameter width = 32;
localparam nr_of_ports = 2;
localparam nr_of_ports = 2;
input [width-1:0] a1, a0;
input [width-1:0] a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
output [width-1:0] dout;
 
 
`define MODULE mux_andor
`define MODULE mux_andor
`BASE`MODULE
`BASE`MODULE
    # ( .width(width), .nr_of_ports(nr_of_ports))
    # ( .width(width), .nr_of_ports(nr_of_ports))
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
`undef MODULE
`undef MODULE
 
 
endmodule
endmodule
`endif
`endif
 
 
`ifdef MUX3_ANDOR
`ifdef MUX3_ANDOR
`define MODULE mux3_andor
`define MODULE mux3_andor
module `BASE`MODULE ( a2, a1, a0, sel, dout);
module `BASE`MODULE ( a2, a1, a0, sel, dout);
`undef MODULE
`undef MODULE
 
 
parameter width = 32;
parameter width = 32;
localparam nr_of_ports = 3;
localparam nr_of_ports = 3;
input [width-1:0] a2, a1, a0;
input [width-1:0] a2, a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
output [width-1:0] dout;
 
 
`define MODULE mux_andor
`define MODULE mux_andor
`BASE`MODULE
`BASE`MODULE
    # ( .width(width), .nr_of_ports(nr_of_ports))
    # ( .width(width), .nr_of_ports(nr_of_ports))
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
`undef MODULE
`undef MODULE
endmodule
endmodule
`endif
`endif
 
 
`ifdef MUX4_ANDOR
`ifdef MUX4_ANDOR
`define MODULE mux4_andor
`define MODULE mux4_andor
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
`undef MODULE
`undef MODULE
 
 
parameter width = 32;
parameter width = 32;
localparam nr_of_ports = 4;
localparam nr_of_ports = 4;
input [width-1:0] a3, a2, a1, a0;
input [width-1:0] a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
output [width-1:0] dout;
 
 
`define MODULE mux_andor
`define MODULE mux_andor
`BASE`MODULE
`BASE`MODULE
    # ( .width(width), .nr_of_ports(nr_of_ports))
    # ( .width(width), .nr_of_ports(nr_of_ports))
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
`undef MODULE
`undef MODULE
 
 
endmodule
endmodule
`endif
`endif
 
 
`ifdef MUX5_ANDOR
`ifdef MUX5_ANDOR
`define MODULE mux5_andor
`define MODULE mux5_andor
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
`undef MODULE
`undef MODULE
 
 
parameter width = 32;
parameter width = 32;
localparam nr_of_ports = 5;
localparam nr_of_ports = 5;
input [width-1:0] a4, a3, a2, a1, a0;
input [width-1:0] a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
output [width-1:0] dout;
 
 
`define MODULE mux_andor
`define MODULE mux_andor
`BASE`MODULE
`BASE`MODULE
    # ( .width(width), .nr_of_ports(nr_of_ports))
    # ( .width(width), .nr_of_ports(nr_of_ports))
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
`undef MODULE
`undef MODULE
 
 
endmodule
endmodule
`endif
`endif
 
 
`ifdef MUX6_ANDOR
`ifdef MUX6_ANDOR
`define MODULE mux6_andor
`define MODULE mux6_andor
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
`undef MODULE
`undef MODULE
 
 
parameter width = 32;
parameter width = 32;
localparam nr_of_ports = 6;
localparam nr_of_ports = 6;
input [width-1:0] a5, a4, a3, a2, a1, a0;
input [width-1:0] a5, a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
output [width-1:0] dout;
 
 
`define MODULE mux_andor
`define MODULE mux_andor
`BASE`MODULE
`BASE`MODULE
    # ( .width(width), .nr_of_ports(nr_of_ports))
    # ( .width(width), .nr_of_ports(nr_of_ports))
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
`undef MODULE
`undef MODULE
 
 
endmodule
endmodule
`endif
`endif
 
 
`ifdef PARITY
`ifdef PARITY
 
 
`define MODULE parity_generate
`define MODULE parity_generate
module `BASE`MODULE (data, parity);
module `BASE`MODULE (data, parity);
`undef MODULE
`undef MODULE
parameter word_size = 32;
parameter word_size = 32;
parameter chunk_size = 8;
parameter chunk_size = 8;
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
input [word_size-1:0] data;
input [word_size-1:0] data;
output reg [word_size/chunk_size-1:0] parity;
output reg [word_size/chunk_size-1:0] parity;
integer i,j;
integer i,j;
always @ (data)
always @ (data)
for (i=0;i<word_size/chunk_size;i=i+1) begin
for (i=0;i<word_size/chunk_size;i=i+1) begin
    parity[i] = parity_type;
    parity[i] = parity_type;
    for (j=0;j<chunk_size;j=j+1) begin
    for (j=0;j<chunk_size;j=j+1) begin
        parity[i] = data[i*chunk_size+j] ^ parity[i];
        parity[i] = data[i*chunk_size+j] ^ parity[i];
    end
    end
end
end
endmodule
endmodule
 
 
`define MODULE parity_check
`define MODULE parity_check
module `BASE`MODULE( data, parity, parity_error);
module `BASE`MODULE( data, parity, parity_error);
`undef MODULE
`undef MODULE
parameter word_size = 32;
parameter word_size = 32;
parameter chunk_size = 8;
parameter chunk_size = 8;
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
input [word_size-1:0] data;
input [word_size-1:0] data;
input [word_size/chunk_size-1:0] parity;
input [word_size/chunk_size-1:0] parity;
output parity_error;
output parity_error;
reg [word_size/chunk_size-1:0] error_flag;
reg [word_size/chunk_size-1:0] error_flag;
integer i,j;
integer i,j;
always @ (data or parity)
always @ (data or parity)
for (i=0;i<word_size/chunk_size;i=i+1) begin
for (i=0;i<word_size/chunk_size;i=i+1) begin
    error_flag[i] = parity[i] ^ parity_type;
    error_flag[i] = parity[i] ^ parity_type;
    for (j=0;j<chunk_size;j=j+1) begin
    for (j=0;j<chunk_size;j=j+1) begin
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
    end
    end
end
end
assign parity_error = |error_flag;
assign parity_error = |error_flag;
endmodule
endmodule
 
 
`endif//////////////////////////////////////////////////////////////////////
`endif//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  IO functions                                                ////
////  IO functions                                                ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  IO functions such as IOB flip-flops                         ////
////  IO functions such as IOB flip-flops                         ////
////                                                              ////
////                                                              ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   -                                                          ////
////   -                                                          ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
`timescale 1ns/1ns
`timescale 1ns/1ns
`ifdef O_DFF
`ifdef O_DFF
`define MODULE o_dff
`define MODULE o_dff
module `BASE`MODULE (d_i, o_pad, clk, rst);
module `BASE`MODULE (d_i, o_pad, clk, rst);
`undef MODULE
`undef MODULE
parameter width = 1;
parameter width = 1;
parameter reset_value = {width{1'b0}};
parameter reset_value = {width{1'b0}};
input  [width-1:0]  d_i;
input  [width-1:0]  d_i;
output [width-1:0] o_pad;
output [width-1:0] o_pad;
input clk, rst;
input clk, rst;
wire [width-1:0] d_i_int `SYN_KEEP;
wire [width-1:0] d_i_int `SYN_KEEP;
reg  [width-1:0] o_pad_int;
reg  [width-1:0] o_pad_int;
assign d_i_int = d_i;
assign d_i_int = d_i;
genvar i;
genvar i;
generate
generate
for (i=0;i<width;i=i+1) begin
for (i=0;i<width;i=i+1) begin
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        o_pad_int[i] <= reset_value[i];
        o_pad_int[i] <= reset_value[i];
    else
    else
        o_pad_int[i] <= d_i_int[i];
        o_pad_int[i] <= d_i_int[i];
    assign #1 o_pad[i] = o_pad_int[i];
    assign #1 o_pad[i] = o_pad_int[i];
end
end
endgenerate
endgenerate
endmodule
endmodule
`endif
`endif
 
 
`timescale 1ns/1ns
`timescale 1ns/1ns
`ifdef IO_DFF_OE
`ifdef IO_DFF_OE
`define MODULE io_dff_oe
`define MODULE io_dff_oe
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
`undef MODULE
`undef MODULE
parameter width = 1;
parameter width = 1;
input  [width-1:0] d_o;
input  [width-1:0] d_o;
output reg [width-1:0] d_i;
output reg [width-1:0] d_i;
input oe;
input oe;
inout [width-1:0] io_pad;
inout [width-1:0] io_pad;
input clk, rst;
input clk, rst;
wire [width-1:0] oe_d `SYN_KEEP;
wire [width-1:0] oe_d `SYN_KEEP;
reg [width-1:0] oe_q;
reg [width-1:0] oe_q;
reg [width-1:0] d_o_q;
reg [width-1:0] d_o_q;
assign oe_d = {width{oe}};
assign oe_d = {width{oe}};
genvar i;
genvar i;
generate
generate
for (i=0;i<width;i=i+1) begin
for (i=0;i<width;i=i+1) begin
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        oe_q[i] <= 1'b0;
        oe_q[i] <= 1'b0;
    else
    else
        oe_q[i] <= oe_d[i];
        oe_q[i] <= oe_d[i];
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        d_o_q[i] <= 1'b0;
        d_o_q[i] <= 1'b0;
    else
    else
        d_o_q[i] <= d_o[i];
        d_o_q[i] <= d_o[i];
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        d_i[i] <= 1'b0;
        d_i[i] <= 1'b0;
    else
    else
        d_i[i] <= io_pad[i];
        d_i[i] <= io_pad[i];
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
end
end
endgenerate
endgenerate
endmodule
endmodule
`endif
`endif
`ifdef CNT_BIN
`ifdef CNT_BIN
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////  counter                                                     ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// binary counter
// binary counter
 
 
`define MODULE cnt_bin
`define MODULE cnt_bin
module `BASE`MODULE (
module `BASE`MODULE (
`undef MODULE
`undef MODULE
 q, rst, clk);
 q, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   output [length:1] q;
   output [length:1] q;
   input rst;
   input rst;
   input clk;
   input clk;
 
 
   parameter clear_value = 0;
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter set_value = 1;
   parameter wrap_value = 0;
   parameter wrap_value = 0;
   parameter level1_value = 15;
   parameter level1_value = 15;
 
 
   reg  [length:1] qi;
   reg  [length:1] qi;
   wire [length:1] q_next;
   wire [length:1] q_next;
   assign q_next = qi + {{length-1{1'b0}},1'b1};
   assign q_next = qi + {{length-1{1'b0}},1'b1};
 
 
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       qi <= {length{1'b0}};
       qi <= {length{1'b0}};
     else
     else
       qi <= q_next;
       qi <= q_next;
 
 
   assign q = qi;
   assign q = qi;
 
 
endmodule
endmodule
`endif
`endif
`ifdef CNT_BIN_CLEAR
`ifdef CNT_BIN_CLEAR
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////  counter                                                     ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// binary counter
// binary counter
 
 
`define MODULE cnt_bin_clear
`define MODULE cnt_bin_clear
module `BASE`MODULE (
module `BASE`MODULE (
`undef MODULE
`undef MODULE
 clear, q, rst, clk);
 clear, q, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   input clear;
   input clear;
   output [length:1] q;
   output [length:1] q;
   input rst;
   input rst;
   input clk;
   input clk;
 
 
   parameter clear_value = 0;
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter set_value = 1;
   parameter wrap_value = 0;
   parameter wrap_value = 0;
   parameter level1_value = 15;
   parameter level1_value = 15;
 
 
   reg  [length:1] qi;
   reg  [length:1] qi;
   wire [length:1] q_next;
   wire [length:1] q_next;
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
 
 
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       qi <= {length{1'b0}};
       qi <= {length{1'b0}};
     else
     else
       qi <= q_next;
       qi <= q_next;
 
 
   assign q = qi;
   assign q = qi;
 
 
endmodule
endmodule
`endif
`endif
`ifdef CNT_BIN_CE
`ifdef CNT_BIN_CE
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////  counter                                                     ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// binary counter
// binary counter
 
 
`define MODULE cnt_bin_ce
`define MODULE cnt_bin_ce
module `BASE`MODULE (
module `BASE`MODULE (
`undef MODULE
`undef MODULE
 cke, q, rst, clk);
 cke, q, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   output [length:1] q;
   output [length:1] q;
   input rst;
   input rst;
   input clk;
   input clk;
 
 
   parameter clear_value = 0;
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter set_value = 1;
   parameter wrap_value = 0;
   parameter wrap_value = 0;
   parameter level1_value = 15;
   parameter level1_value = 15;
 
 
   reg  [length:1] qi;
   reg  [length:1] qi;
   wire [length:1] q_next;
   wire [length:1] q_next;
   assign q_next = qi + {{length-1{1'b0}},1'b1};
   assign q_next = qi + {{length-1{1'b0}},1'b1};
 
 
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       qi <= {length{1'b0}};
       qi <= {length{1'b0}};
     else
     else
     if (cke)
     if (cke)
       qi <= q_next;
       qi <= q_next;
 
 
   assign q = qi;
   assign q = qi;
 
 
endmodule
endmodule
`endif
`endif
`ifdef CNT_BIN_CE_CLEAR
`ifdef CNT_BIN_CE_CLEAR
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////  counter                                                     ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// binary counter
// binary counter
 
 
`define MODULE cnt_bin_ce_clear
`define MODULE cnt_bin_ce_clear
module `BASE`MODULE (
module `BASE`MODULE (
`undef MODULE
`undef MODULE
 clear, cke, q, rst, clk);
 clear, cke, q, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   input clear;
   input clear;
   input cke;
   input cke;
   output [length:1] q;
   output [length:1] q;
   input rst;
   input rst;
   input clk;
   input clk;
 
 
   parameter clear_value = 0;
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter set_value = 1;
   parameter wrap_value = 0;
   parameter wrap_value = 0;
   parameter level1_value = 15;
   parameter level1_value = 15;
 
 
   reg  [length:1] qi;
   reg  [length:1] qi;
   wire [length:1] q_next;
   wire [length:1] q_next;
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
 
 
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       qi <= {length{1'b0}};
       qi <= {length{1'b0}};
     else
     else
     if (cke)
     if (cke)
       qi <= q_next;
       qi <= q_next;
 
 
   assign q = qi;
   assign q = qi;
 
 
endmodule
endmodule
`endif
`endif
`ifdef CNT_BIN_CE_CLEAR_L1_L2
`ifdef CNT_BIN_CE_CLEAR_L1_L2
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////  counter                                                     ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// binary counter
// binary counter
 
 
`define MODULE cnt_bin_ce_clear_l1_l2
`define MODULE cnt_bin_ce_clear_l1_l2
module `BASE`MODULE (
module `BASE`MODULE (
`undef MODULE
`undef MODULE
 clear, cke, q, level1, level2, rst, clk);
 clear, cke, q, level1, level2, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   input clear;
   input clear;
   input cke;
   input cke;
   output [length:1] q;
   output [length:1] q;
   output reg level1;
   output reg level1;
   output reg level2;
   output reg level2;
   input rst;
   input rst;
   input clk;
   input clk;
 
 
   parameter clear_value = 0;
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter set_value = 1;
   parameter wrap_value = 15;
   parameter wrap_value = 15;
   parameter level1_value = 8;
   parameter level1_value = 8;
   parameter level2_value = 15;
   parameter level2_value = 15;
 
 
   wire rew;
   wire rew;
   assign rew = 1'b0;
   assign rew = 1'b0;
   reg  [length:1] qi;
   reg  [length:1] qi;
   wire [length:1] q_next;
   wire [length:1] q_next;
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
 
 
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       qi <= {length{1'b0}};
       qi <= {length{1'b0}};
     else
     else
     if (cke)
     if (cke)
       qi <= q_next;
       qi <= q_next;
 
 
   assign q = qi;
   assign q = qi;
 
 
 
 
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        level1 <= 1'b0;
        level1 <= 1'b0;
    else
    else
    if (cke)
    if (cke)
    if (clear)
    if (clear)
        level1 <= 1'b0;
        level1 <= 1'b0;
    else if (q_next == level1_value)
    else if (q_next == level1_value)
        level1 <= 1'b1;
        level1 <= 1'b1;
    else if (qi == level1_value & rew)
    else if (qi == level1_value & rew)
        level1 <= 1'b0;
        level1 <= 1'b0;
 
 
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        level2 <= 1'b0;
        level2 <= 1'b0;
    else
    else
    if (cke)
    if (cke)
    if (clear)
    if (clear)
        level2 <= 1'b0;
        level2 <= 1'b0;
    else if (q_next == level2_value)
    else if (q_next == level2_value)
        level2 <= 1'b1;
        level2 <= 1'b1;
    else if (qi == level2_value & rew)
    else if (qi == level2_value & rew)
        level2 <= 1'b0;
        level2 <= 1'b0;
endmodule
endmodule
`endif
`endif
`ifdef CNT_BIN_CE_CLEAR_SET_REW
`ifdef CNT_BIN_CE_CLEAR_SET_REW
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////  counter                                                     ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// binary counter
// binary counter
 
 
`define MODULE cnt_bin_ce_clear_set_rew
`define MODULE cnt_bin_ce_clear_set_rew
module `BASE`MODULE (
module `BASE`MODULE (
`undef MODULE
`undef MODULE
 clear, set, cke, rew, q, rst, clk);
 clear, set, cke, rew, q, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   input clear;
   input clear;
   input set;
   input set;
   input cke;
   input cke;
   input rew;
   input rew;
   output [length:1] q;
   output [length:1] q;
   input rst;
   input rst;
   input clk;
   input clk;
 
 
   parameter clear_value = 0;
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter set_value = 1;
   parameter wrap_value = 0;
   parameter wrap_value = 0;
   parameter level1_value = 15;
   parameter level1_value = 15;
 
 
   reg  [length:1] qi;
   reg  [length:1] qi;
   wire  [length:1] q_next, q_next_fw, q_next_rew;
   wire  [length:1] q_next, q_next_fw, q_next_rew;
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
   assign q_next = rew ? q_next_rew : q_next_fw;
   assign q_next = rew ? q_next_rew : q_next_fw;
 
 
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       qi <= {length{1'b0}};
       qi <= {length{1'b0}};
     else
     else
     if (cke)
     if (cke)
       qi <= q_next;
       qi <= q_next;
 
 
   assign q = qi;
   assign q = qi;
 
 
endmodule
endmodule
`endif
`endif
`ifdef CNT_BIN_CE_REW_L1
`ifdef CNT_BIN_CE_REW_L1
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////  counter                                                     ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
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