OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Diff between revs 130 and 131

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 130 Rev 131
Line 6296... Line 6296...
assign we = wbs_cyc_i &  wbs_we_i & wbs_ack_o;
assign we = wbs_cyc_i &  wbs_we_i & wbs_ack_o;
end else if (wbs_mode=="B4") begin : inst_b4
end else if (wbs_mode=="B4") begin : inst_b4
end
end
 
 
endgenerate
endgenerate
 
localparam cache_mem_b_aw =
 
    (dw_s==dw_m) ? aw_slot+aw_offset :
 
    (dw_s==dw_m/2) ? aw_slot+aw_offset+1 :
 
    (dw_s==dw_m/4) ? aw_slot+aw_offset+2 :
 
    (dw_s==dw_m/8) ? aw_slot+aw_offset+3 :
 
    (dw_s==dw_m/16) ? aw_slot+aw_offset+4 :
 
    (dw_s==dw_m*2) ? aw_slot+aw_offset-1 :
 
    (dw_s==dw_m*4) ? aw_slot+aw_offset-2 :
 
    (dw_s==dw_m*8) ? aw_slot+aw_offset-3 :
 
    (dw_s==dw_m*16) ? aw_slot+aw_offset-4 : 0;
 
 
`define MODULE dpram_be_2r2w
`define MODULE dpram_be_2r2w
`BASE`MODULE
`BASE`MODULE
    # ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))
    # ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))
    cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]),   .be_a(wbs_sel_i), .we_a(we), .q_a(wbs_dat_o), .clk_a(wbs_clk),
    cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]),   .be_a(wbs_sel_i), .we_a(we), .q_a(wbs_dat_o), .clk_a(wbs_clk),

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.