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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Diff between revs 137 and 139

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Rev 137 Rev 139
Line 33... Line 33...
`define CNT_SHREG_CE_WRAP
`define CNT_SHREG_CE_WRAP
`define CNT_SHREG_CLEAR
`define CNT_SHREG_CLEAR
`define CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR_WRAP
`define CNT_SHREG_CE_CLEAR_WRAP
 
 
 
`define CNT_BIN
 
`define CNT_BIN_CE
 
`define CNT_BIN_CLEAR
 
`define CNT_BIN_CE_CLEAR
 
`define CNT_BIN_CE_CLEAR_L1_L2
 
`define CNT_BIN_CE_CLEAR_SET_REW
 
`define CNT_BIN_CE_REW_L1
 
`define CNT_BIN_CE_REW_ZQ_L1
 
`define CNT_BIN_CE_REW_Q_ZQ_L1
 
`define CNT_GRAY
 
`define CNT_GRAY_CE
 
`define CNT_GRAY_CE_BIN
 
`define CNT_LFSR_ZQ
 
`define CNT_LFSR_CE
 
`define CNT_LFSR_CE_CLEAR_Q
 
`define CNT_LFSR_CE_Q
 
`define CNT_LFSR_CE_ZQ
 
`define CNT_LFSR_CE_Q_ZQ
 
`define CNT_LFSR_CE_REW_L1
 
 
`define MUX_ANDOR
`define MUX_ANDOR
`define MUX2_ANDOR
`define MUX2_ANDOR
`define MUX3_ANDOR
`define MUX3_ANDOR
`define MUX4_ANDOR
`define MUX4_ANDOR
`define MUX5_ANDOR
`define MUX5_ANDOR
Line 839... Line 859...
`ifdef DFF
`ifdef DFF
`define MODULE dff
`define MODULE dff
module `BASE`MODULE ( d, q, clk, rst);
module `BASE`MODULE ( d, q, clk, rst);
`undef MODULE
`undef MODULE
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = {width{1'b0}};
 
 
        input [width-1:0] d;
        input [width-1:0] d;
        input clk, rst;
        input clk, rst;
        output reg [width-1:0] q;
        output reg [width-1:0] q;
 
 
Line 889... Line 909...
`define MODULE dff_ce
`define MODULE dff_ce
module `BASE`MODULE ( d, ce, q, clk, rst);
module `BASE`MODULE ( d, ce, q, clk, rst);
`undef MODULE
`undef MODULE
 
 
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = {width{1'b0}};
 
 
        input [width-1:0] d;
        input [width-1:0] d;
        input ce, clk, rst;
        input ce, clk, rst;
        output reg [width-1:0] q;
        output reg [width-1:0] q;
 
 
Line 911... Line 931...
`define MODULE dff_ce_clear
`define MODULE dff_ce_clear
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
`undef MODULE
`undef MODULE
 
 
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = {width{1'b0}};
 
 
        input [width-1:0] d;
        input [width-1:0] d;
        input ce, clear, clk, rst;
        input ce, clear, clk, rst;
        output reg [width-1:0] q;
        output reg [width-1:0] q;
 
 
Line 936... Line 956...
`define MODULE dff_ce_set
`define MODULE dff_ce_set
module `BASE`MODULE ( d, ce, set, q, clk, rst);
module `BASE`MODULE ( d, ce, set, q, clk, rst);
`undef MODULE
`undef MODULE
 
 
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = {width{1'b0}};
 
 
        input [width-1:0] d;
        input [width-1:0] d;
        input ce, set, clk, rst;
        input ce, set, clk, rst;
        output reg [width-1:0] q;
        output reg [width-1:0] q;
 
 

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