| Line 24... |
Line 24... |
`define PLL
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`define PLL
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`define MULTS
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`define MULTS
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`define MULTS18X18
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`define MULTS18X18
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`define MULT
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`define MULT
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`define ARITH_UNIT
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`define SHIFT_UNIT_32
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`define SHIFT_UNIT_32
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`define LOGIC_UNIT
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`define LOGIC_UNIT
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`define COUNT_UNIT
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`define EXT_UNIT
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`define CNT_SHREG_WRAP
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`define CNT_SHREG_WRAP
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`define CNT_SHREG_CE_WRAP
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`define CNT_SHREG_CE_WRAP
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`define CNT_SHREG_CLEAR
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`define CNT_SHREG_CLEAR
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`define CNT_SHREG_CE_CLEAR
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`define CNT_SHREG_CE_CLEAR
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| Line 775... |
Line 778... |
`define MODULE pll
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`define MODULE pll
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module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
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module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
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`undef MODULE
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`undef MODULE
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parameter index = 0;
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parameter index = 0;
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parameter number_of_clk = 1;
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parameter number_of_clk = 1;
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parameter period_time_0 = 20000;
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parameter period_time = 20000;
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parameter period_time_1 = 20000;
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parameter clk0_mult_by = 1;
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parameter period_time_2 = 20000;
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parameter clk0_div_by = 1;
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parameter lock_delay = 2000;
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parameter clk1_mult_by = 1;
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parameter clk1_div_by = 1;
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parameter clk2_mult_by = 1;
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parameter clk3_div_by = 1;
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parameter clk3_mult_by = 1;
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parameter clk3_div_by = 1;
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parameter clk4_mult_by = 1;
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parameter clk4_div_by = 1;
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input clk_i, rst_n_i;
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input clk_i, rst_n_i;
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output lock;
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output lock;
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output reg [0:number_of_clk-1] clk_o;
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output reg [0:number_of_clk-1] clk_o;
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output [0:number_of_clk-1] rst_o;
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initial
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clk_o = {number_of_clk{1'b0}};
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always
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always
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#((period_time_0)/2) clk_o[0] <= (!rst_n_i) ? 0 : ~clk_o[0];
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#((period_time*clk0_div_by/clk0_mult_by)/2) clk_o[0] <= (!rst_n_i) ? 1'b0 : ~clk_o[0];
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generate if (number_of_clk > 1)
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generate if (number_of_clk > 1)
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always
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always
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#((period_time_1)/2) clk_o[1] <= (!rst_n_i) ? 0 : ~clk_o[1];
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#((period_time*clk1_div_by/clk1_mult_by)/2) clk_o[1] <= (!rst_n_i) ? 1'b0 : ~clk_o[1];
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endgenerate
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endgenerate
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generate if (number_of_clk > 2)
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generate if (number_of_clk > 2)
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always
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always
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#((period_time_2)/2) clk_o[2] <= (!rst_n_i) ? 0 : ~clk_o[2];
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#((period_time*clk2_div_by/clk2_mult_by)/2) clk_o[2] <= (!rst_n_i) ? 1'b0 : ~clk_o[2];
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endgenerate
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endgenerate
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genvar i;
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generate if (number_of_clk > 3)
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generate for (i=0;i<number_of_clk;i=i+1) begin: clock
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always
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`define MODULE sync_rst
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#((period_time*clk3_div_by/clk3_mult_by)/2) clk_o[3] <= (!rst_n_i) ? 1'b0 : ~clk_o[3];
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`BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
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endgenerate
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`undef MODULE
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end
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generate if (number_of_clk > 4)
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always
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#((period_time*clk4_div_by/clk4_mult_by)/2) clk_o[4] <= (!rst_n_i) ? 1'b0 : ~clk_o[4];
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endgenerate
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endgenerate
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assign #lock_delay lock = rst_n_i;
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assign #lock_delay lock = rst_n_i;
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endmodule
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endmodule
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| Line 1681... |
Line 1695... |
`timescale 1ns/1ns
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`timescale 1ns/1ns
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`define MODULE io_dff_oe
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`define MODULE io_dff_oe
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module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
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module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
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`undef MODULE
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`undef MODULE
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parameter width = 1;
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parameter width = 1;
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parameter reset_value = 1'b0;
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input [width-1:0] d_o;
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input [width-1:0] d_o;
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output reg [width-1:0] d_i;
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output reg [width-1:0] d_i;
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input oe;
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input oe;
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inout [width-1:0] io_pad;
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inout [width-1:0] io_pad;
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input clk, rst;
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input clk, rst;
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| Line 1700... |
Line 1715... |
oe_q[i] <= 1'b0;
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oe_q[i] <= 1'b0;
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else
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else
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oe_q[i] <= oe_d[i];
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oe_q[i] <= oe_d[i];
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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if (rst)
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if (rst)
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d_o_q[i] <= 1'b0;
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d_o_q[i] <= reset_value;
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else
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else
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d_o_q[i] <= d_o[i];
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d_o_q[i] <= d_o[i];
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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if (rst)
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if (rst)
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d_i[i] <= 1'b0;
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d_i[i] <= reset_value;
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else
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else
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d_i[i] <= io_pad[i];
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d_i[i] <= io_pad[i];
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assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
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assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
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end
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end
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endgenerate
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endgenerate
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