OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Diff between revs 140 and 141

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 140 Rev 141
Line 172... Line 172...
 
 
`ifdef WB_DPRAM
`ifdef WB_DPRAM
`ifndef WB_ADR_INC
`ifndef WB_ADR_INC
`define WB_ADR_INC
`define WB_ADR_INC
`endif
`endif
 
`ifndef DFF
 
`define DFF
 
`endif
`ifndef DPRAM_BE_2R2W
`ifndef DPRAM_BE_2R2W
`define DPRAM_BE_2R2W
`define DPRAM_BE_2R2W
`endif
`endif
`endif
`endif
 
 
Line 4380... Line 4383...
 
 
    generate
    generate
    if (debug==1) begin : debug_we
    if (debug==1) begin : debug_we
        always @ (posedge clk_a)
        always @ (posedge clk_a)
        if (we_a)
        if (we_a)
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
            $display ("Debug: Value %h written on port A at address %h : time %t", d_a, adr_a, $time);
        always @ (posedge clk_b)
        always @ (posedge clk_b)
        if (we_b)
        if (we_b)
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
            $display ("Debug: Value %h written on port B at address %h : time %t", d_b, adr_b, $time);
    end
    end
    endgenerate
    endgenerate
 
 
 
 
`ifdef SYSTEMVERILOG
`ifdef SYSTEMVERILOG

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.