OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Diff between revs 142 and 143

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 142 Rev 143
Line 4999... Line 4999...
`undef MODULE
`undef MODULE
    a1, a2, a3, wd3, we3, rd1, rd2, clk
    a1, a2, a3, wd3, we3, rd1, rd2, clk
);
);
parameter data_width = 32;
parameter data_width = 32;
parameter addr_width = 5;
parameter addr_width = 5;
 
parameter debug = 0;
input [addr_width-1:0] a1, a2, a3;
input [addr_width-1:0] a1, a2, a3;
input [data_width-1:0] wd3;
input [data_width-1:0] wd3;
input we3;
input we3;
output [data_width-1:0] rd1, rd2;
output [data_width-1:0] rd1, rd2;
input clk;
input clk;
 
 
 
generate
 
if (debug==1) begin : debug_we
 
    always @ (posedge clk)
 
        if (we)
 
            $display ("Value %h written at register %h : time %t", d, adr, $time);
 
end
 
endgenerate
 
 
`ifdef ACTEL
`ifdef ACTEL
reg [data_width-1:0] wd3_reg;
reg [data_width-1:0] wd3_reg;
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
reg we3_reg;
reg we3_reg;
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.