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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Diff between revs 147 and 148

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Rev 147 Rev 148
Line 5042... Line 5042...
        .clk_b(clk) );
        .clk_b(clk) );
`undef MODULE
`undef MODULE
 
 
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
if (rst)
if (rst)
    {sel1, sel2, wreg} <= {1'b0,1'b0,{data_width{1'b0}}};
    {sel1, sel2, wreg} <= {1'b0,1'b0,{dw{1'b0}}};
else
else
    {sel1,sel2,wreg} <= {we3 & a1==a3, we3 & a2==a3,wd3};
    {sel1,sel2,wreg} <= {we3 & a1==a3, we3 & a2==a3,wd3};
assign rd1 = (sel1) ? wreg : rd1mem;
assign rd1 = (sel1) ? wreg : rd1mem;
assign rd2 = (sel2) ? wreg : rd2mem;
assign rd2 = (sel2) ? wreg : rd2mem;
 
 

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