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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Diff between revs 151 and 152

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Rev 151 Rev 152
Line 7462... Line 7462...
    //opcode_ror: dout = not yet implemented
    //opcode_ror: dout = not yet implemented
    default: dout = din << s;
    default: dout = din << s;
    endcase
    endcase
 
 
end
end
engenerate
endgenerate
 
 
endmodule
endmodule
`endif
`endif
 
 
`ifdef LOGIC_UNIT
`ifdef LOGIC_UNIT

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