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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Diff between revs 18 and 21

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Rev 18 Rev 21
Line 69... Line 69...
gbuf gbuf_i0 ( .CLK(i), .GL(o));
gbuf gbuf_i0 ( .CLK(i), .GL(o));
`endif
`endif
endmodule
endmodule
`else
`else
`ifdef ALTERA
`ifdef ALTERA
altera
//altera
`else
`else
 
 
`timescale 1 ns/100 ps
`timescale 1 ns/100 ps
module vl_gbuf ( i, o);
module vl_gbuf ( i, o);
input i;
input i;
Line 645... Line 645...
parameter nr_of_ports = 4;
parameter nr_of_ports = 4;
input [width-1:0] a3, a2, a1, a0;
input [width-1:0] a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
output reg [width-1:0] dout;
 
 
reg [width-1:0] tmp [nr_of_ports-1:0];
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
integer i;
 
 
// and
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[1] = {width{sel[1]}} & a1;
Line 667... Line 667...
parameter nr_of_ports = 5;
parameter nr_of_ports = 5;
input [width-1:0] a4, a3, a2, a1, a0;
input [width-1:0] a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
output reg [width-1:0] dout;
 
 
reg [width-1:0] tmp [nr_of_ports-1:0];
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
integer i;
 
 
// and
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[1] = {width{sel[1]}} & a1;
Line 690... Line 690...
parameter nr_of_ports = 6;
parameter nr_of_ports = 6;
input [width-1:0] a5, a4, a3, a2, a1, a0;
input [width-1:0] a5, a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
output reg [width-1:0] dout;
 
 
reg [width-1:0] tmp [nr_of_ports-1:0];
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
integer i;
 
 
// and
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[1] = {width{sel[1]}} & a1;
Line 2144... Line 2144...
output                  fifo_empty;
output                  fifo_empty;
input                   rd_clk;
input                   rd_clk;
input                   rd_rst;
input                   rd_rst;
 
 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
 
/*
vl_fifo_1r1w_async (
vl_fifo_1r1w_async (
    d, wr, fifo_full, wr_clk, wr_rst,
    d, wr, fifo_full, wr_clk, wr_rst,
    q, rd, fifo_empty, rd_clk, rd_rst
    q, rd, fifo_empty, rd_clk, rd_rst
    );
    );
 
*/
vl_cnt_gray_ce_bin
vl_cnt_gray_ce_bin
    # ( .length(addr_width))
    # ( .length(addr_width))
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
 
 
vl_cnt_gray_ce_bin
vl_cnt_gray_ce_bin

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