Line 67... |
Line 67... |
assign o=i;
|
assign o=i;
|
`else
|
`else
|
gbuf gbuf_i0 ( .CLK(i), .GL(o));
|
gbuf gbuf_i0 ( .CLK(i), .GL(o));
|
`endif
|
`endif
|
endmodule
|
endmodule
|
|
|
`else
|
`else
|
|
|
`ifdef ALTERA
|
`ifdef ALTERA
|
//altera
|
//altera
|
|
module vl_gbuf ( i, o);
|
|
input i;
|
|
output o;
|
|
assign o = i;
|
|
endmodule
|
|
|
`else
|
`else
|
|
|
`timescale 1 ns/100 ps
|
`timescale 1 ns/100 ps
|
module vl_gbuf ( i, o);
|
module vl_gbuf ( i, o);
|
input i;
|
input i;
|
Line 93... |
Line 101... |
reg [1:0] tmp;
|
reg [1:0] tmp;
|
always @ (posedge clk or negedge rst_n_i)
|
always @ (posedge clk or negedge rst_n_i)
|
if (!rst_n_i)
|
if (!rst_n_i)
|
tmp <= 2'b11;
|
tmp <= 2'b11;
|
else
|
else
|
tmp <= {1'b0,tmp[0]};
|
tmp <= {1'b0,tmp[1]};
|
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
|
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
|
endmodule
|
endmodule
|
|
|
// vl_pll
|
// vl_pll
|
`ifdef ACTEL
|
`ifdef ACTEL
|
Line 233... |
Line 241... |
generate if (number_of_clk > 2)
|
generate if (number_of_clk > 2)
|
always
|
always
|
#((period_time_2)/2) clk_o[2] <= (!rst_n_i) ? 0 : ~clk_o[2];
|
#((period_time_2)/2) clk_o[2] <= (!rst_n_i) ? 0 : ~clk_o[2];
|
endgenerate
|
endgenerate
|
|
|
|
generate if (number_of_clk > 3)
|
always
|
always
|
#((period_time_3)/2) clk_o[3] <= (!rst_n_i) ? 0 : ~clk_o[3];
|
#((period_time_3)/2) clk_o[3] <= (!rst_n_i) ? 0 : ~clk_o[3];
|
endgenerate
|
endgenerate
|
|
|
|
generate if (number_of_clk > 4)
|
always
|
always
|
#((period_time_4)/2) clk_o[4] <= (!rst_n_i) ? 0 : ~clk_o[4];
|
#((period_time_4)/2) clk_o[4] <= (!rst_n_i) ? 0 : ~clk_o[4];
|
endgenerate
|
endgenerate
|
|
|
genvar i;
|
genvar i;
|
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
|
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
|
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
|
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
assign #lock_delay lock = rst_n_i;
|
//assign #lock_delay lock = rst_n_i;
|
|
assign lock = rst_n_i;
|
|
|
endmodule
|
endmodule
|
`else
|
`else
|
generate if (number_of_clk==1 & index==0) begin
|
|
pll0 pll_i0 (.areset(1'b1), .inclk(clk_i), .locked(lock), .c0(clk_o[0]));
|
|
end
|
|
endgenerate // index==0
|
|
generate if (number_of_clk==1 & index==1) begin
|
|
pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
|
|
end
|
|
endgenerate // index==1
|
|
generate if (number_of_clk==1 & index==2) begin
|
|
pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
|
|
end
|
|
endgenerate // index==2
|
|
generate if (number_of_clk==1 & index==3) begin
|
|
pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
|
|
end
|
|
endgenerate // index==3
|
|
|
|
generate if (number_of_clk==2 & index==0) begin
|
`ifdef VL_PLL0
|
pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
|
`ifdef VL_PLL0_CLK1
|
end
|
pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
|
endgenerate // index==0
|
`endif
|
generate if (number_of_clk==2 & index==1) begin
|
`ifdef VL_PLL0_CLK2
|
pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
|
pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
|
end
|
`endif
|
endgenerate // index==1
|
`ifdef VL_PLL0_CLK3
|
generate if (number_of_clk==2 & index==2) begin
|
pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
|
pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
|
`endif
|
end
|
`ifdef VL_PLL0_CLK4
|
endgenerate // index==2
|
pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
|
generate if (number_of_clk==2 & index==3) begin
|
`endif
|
pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
|
`ifdef VL_PLL0_CLK5
|
end
|
pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
|
endgenerate // index==3
|
`endif
|
|
`endif
|
|
|
generate if (number_of_clk==3 & index==0) begin
|
`ifdef VL_PLL1
|
pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
|
`ifdef VL_PLL1_CLK1
|
end
|
pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
|
endgenerate // index==0
|
`endif
|
generate if (number_of_clk==3 & index==1) begin
|
`ifdef VL_PLL1_CLK2
|
pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
|
pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
|
end
|
`endif
|
endgenerate // index==1
|
`ifdef VL_PLL1_CLK3
|
generate if (number_of_clk==3 & index==2) begin
|
pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
|
pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
|
`endif
|
end
|
`ifdef VL_PLL1_CLK4
|
endgenerate // index==2
|
pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
|
generate if (number_of_clk==3 & index==3) begin
|
`endif
|
pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
|
`ifdef VL_PLL1_CLK5
|
end
|
pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
|
endgenerate // index==3
|
`endif
|
|
`endif
|
|
|
generate if (number_of_clk==4 & index==0) begin
|
`ifdef VL_PLL2
|
pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
|
`ifdef VL_PLL2_CLK1
|
end
|
pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
|
endgenerate // index==0
|
`endif
|
generate if (number_of_clk==4 & index==1) begin
|
`ifdef VL_PLL2_CLK2
|
pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3]));
|
pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
|
end
|
`endif
|
endgenerate // index==1
|
`ifdef VL_PLL2_CLK3
|
generate if (number_of_clk==4 & index==2) begin
|
pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
|
pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3]));
|
`endif
|
end
|
`ifdef VL_PLL2_CLK4
|
endgenerate // index==2
|
pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
|
generate if (number_of_clk==4 & index==3) begin
|
`endif
|
pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3]));
|
`ifdef VL_PLL2_CLK5
|
end
|
pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
|
endgenerate // index==3
|
`endif
|
|
`endif
|
|
|
generate if (number_of_clk==5 & index==0) begin
|
`ifdef VL_PLL3
|
pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3], .c4(clk_o[4]));
|
`ifdef VL_PLL3_CLK1
|
end
|
pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
|
endgenerate // index==0
|
`endif
|
generate if (number_of_clk==5 & index==1) begin
|
`ifdef VL_PLL3_CLK2
|
pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3], .c4(clk_o[4]));
|
pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
|
end
|
`endif
|
endgenerate // index==1
|
`ifdef VL_PLL3_CLK3
|
generate if (number_of_clk==5 & index==2) begin
|
pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
|
pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3], .c4(clk_o[4]));
|
`endif
|
end
|
`ifdef VL_PLL3_CLK4
|
endgenerate // index==2
|
pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
|
generate if (number_of_clk==5 & index==3) begin
|
`endif
|
pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3], .c4(clk_o[4]));
|
`ifdef VL_PLL3_CLK5
|
end
|
pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
|
endgenerate // index==3
|
`endif
|
|
`endif
|
|
|
genvar i;
|
genvar i;
|
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
|
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
|
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
|
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
|
end
|
end
|
endgenerate
|
endgenerate
|
endmodule
|
endmodule
|
`endif
|
`endif
|
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
Line 3496... |
Line 3495... |
parameter wbs_data = 1'b1;
|
parameter wbs_data = 1'b1;
|
|
|
parameter wbm_adr0 = 2'b00;
|
parameter wbm_adr0 = 2'b00;
|
parameter wbm_adr1 = 2'b01;
|
parameter wbm_adr1 = 2'b01;
|
parameter wbm_data = 2'b10;
|
parameter wbm_data = 2'b10;
|
|
parameter wbm_data_wait = 2'b11;
|
|
|
reg [1:0] wbs_bte_reg;
|
reg [1:0] wbs_bte_reg;
|
reg wbs;
|
reg wbs;
|
wire wbs_eoc_alert, wbm_eoc_alert;
|
wire wbs_eoc_alert, wbm_eoc_alert;
|
reg wbs_eoc, wbm_eoc;
|
reg wbs_eoc, wbm_eoc;
|
Line 3579... |
Line 3579... |
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
if (wbm_rst)
|
if (wbm_rst)
|
wbm <= wbm_adr0;
|
wbm <= wbm_adr0;
|
else
|
else
|
if ((wbm==wbm_adr0 & !b_fifo_empty) |
|
/*
|
(wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
|
if ((wbm==wbm_adr0 & !b_fifo_empty) |
|
(wbm==wbm_adr1 & !wbm_we_o) |
|
(wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
|
(wbm==wbm_data & wbm_ack_i & wbm_eoc))
|
(wbm==wbm_adr1 & !wbm_we_o) |
|
wbm <= {wbm[0],!(wbm[1] ^ wbm[0])}; // count sequence 00,01,10
|
(wbm==wbm_data & wbm_ack_i & wbm_eoc))
|
|
wbm <= {wbm[0],!(wbm[1] ^ wbm[0])}; // count sequence 00,01,10
|
|
*/
|
|
case (wbm)
|
|
wbm_adr0:
|
|
if (!b_fifo_empty)
|
|
wbm <= wbm_adr1;
|
|
wbm_adr1:
|
|
if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
|
|
wbm <= wbm_data;
|
|
wbm_data:
|
|
if (wbm_ack_i & wbm_eoc)
|
|
wbm <= wbm_adr0;
|
|
else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
|
|
wbm <= wbm_data_wait;
|
|
wbm_data_wait:
|
|
if (!b_fifo_empty)
|
|
wbm <= wbm_data;
|
|
endcase
|
|
|
assign b_d = {wbm_dat_i,4'b1111};
|
assign b_d = {wbm_dat_i,4'b1111};
|
assign b_wr = !wbm_we_o & wbm_ack_i;
|
assign b_wr = !wbm_we_o & wbm_ack_i;
|
assign b_rd_adr = (wbm==wbm_adr0 & !b_fifo_empty);
|
assign b_rd_adr = (wbm==wbm_adr0 & !b_fifo_empty);
|
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
|
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
|
(wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
|
(wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
|
|
(wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
|
1'b0;
|
1'b0;
|
assign b_rd = b_rd_adr | b_rd_data;
|
assign b_rd = b_rd_adr | b_rd_data;
|
|
|
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
|
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
|
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
|
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
|
Line 3606... |
Line 3625... |
.clear(wbm_eoc),
|
.clear(wbm_eoc),
|
.q(wbm_count),
|
.q(wbm_count),
|
.rst(wbm_rst),
|
.rst(wbm_rst),
|
.clk(wbm_clk));
|
.clk(wbm_clk));
|
|
|
assign wbm_cyc_o = wbm==wbm_data;
|
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
|
assign wbm_stb_o = (wbm==wbm_data & wbm_we_o) ? !b_fifo_empty :
|
assign wbm_stb_o = (wbm==wbm_data);
|
(wbm==wbm_data) ? 1'b1 :
|
|
1'b0;
|
|
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
if (wbm_rst)
|
if (wbm_rst)
|
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
|
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
|
else begin
|
else begin
|
Line 3656... |
Line 3673... |
|
|
parameter adr_hi = 31;
|
parameter adr_hi = 31;
|
parameter adr_lo = 28;
|
parameter adr_lo = 28;
|
parameter adr_sel = 4'hf;
|
parameter adr_sel = 4'hf;
|
parameter addr_width = 5;
|
parameter addr_width = 5;
|
|
/*
|
`ifndef BOOT_ROM
|
`ifndef BOOT_ROM
|
`define BOOT_ROM "boot_rom.v"
|
`define BOOT_ROM "boot_rom.v"
|
`endif
|
`endif
|
|
*/
|
input [adr_hi:2] wb_adr_i;
|
input [adr_hi:2] wb_adr_i;
|
input wb_stb_i;
|
input wb_stb_i;
|
input wb_cyc_i;
|
input wb_cyc_i;
|
output [31:0] wb_dat_o;
|
output [31:0] wb_dat_o;
|
output wb_ack_o;
|
output wb_ack_o;
|
Line 3681... |
Line 3698... |
always @ (posedge wb_clk or posedge wb_rst)
|
always @ (posedge wb_clk or posedge wb_rst)
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if (wb_rst)
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if (wb_rst)
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wb_dat <= 32'h15000000;
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wb_dat <= 32'h15000000;
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else
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else
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case (wb_adr_i[addr_width-1:2])
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case (wb_adr_i[addr_width-1:2])
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`ifdef BOOT_ROM
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`include `BOOT_ROM
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`include `BOOT_ROM
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`endif
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/*
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/*
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// Zero r0 and jump to 0x00000100
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// Zero r0 and jump to 0x00000100
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0 : wb_dat <= 32'h18000000;
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0 : wb_dat <= 32'h18000000;
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1 : wb_dat <= 32'hA8200000;
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1 : wb_dat <= 32'hA8200000;
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2 : wb_dat <= 32'hA8C00100;
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2 : wb_dat <= 32'hA8C00100;
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Line 3739... |
Line 3758... |
input wbsb_clk, wbsb_rst;
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input wbsb_clk, wbsb_rst;
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|
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wire wbsa_dat_tmp, wbsb_dat_tmp;
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wire wbsa_dat_tmp, wbsb_dat_tmp;
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|
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vl_dpram_2r2w # (
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vl_dpram_2r2w # (
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.data_width(data_width), addr_width(addr_width) )
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.data_width(data_width), .addr_width(addr_width) )
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dpram0(
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dpram0(
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.d_a(wbsa_dat_i),
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.d_a(wbsa_dat_i),
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.q_a(wbsa_dat_tmp),
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.q_a(wbsa_dat_tmp),
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.adr_a(wbsa_adr_i),
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.adr_a(wbsa_adr_i),
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.we_a(wbsa_we_i),
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.we_a(wbsa_we_i),
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Line 3752... |
Line 3771... |
.q_b(wbsb_dat_tmp),
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.q_b(wbsb_dat_tmp),
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.adr_b(wbsb_adr_i),
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.adr_b(wbsb_adr_i),
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.we_b(wbsb_we_i),
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.we_b(wbsb_we_i),
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.clk_b(wbsb_clk) );
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.clk_b(wbsb_clk) );
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|
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if (dat_o_mask_a==1) generate
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generate if (dat_o_mask_a==1)
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assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
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assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
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endgenerate
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endgenerate
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if (dat_o_mask_a==0) generate
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generate if (dat_o_mask_a==0)
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assign wbsa_dat_o = wbsa_dat_tmp;
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assign wbsa_dat_o = wbsa_dat_tmp;
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endgenerate
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endgenerate
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|
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if (dat_o_mask_b==1) generate
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generate if (dat_o_mask_b==1)
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assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
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assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
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endgenerate
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endgenerate
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if (dat_o_mask_b==0) generate
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generate if (dat_o_mask_b==0)
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assign wbsb_dat_o = wbsb_dat_tmp;
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assign wbsb_dat_o = wbsb_dat_tmp;
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endgenerate
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endgenerate
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|
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vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
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vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
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vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
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vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
|