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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile library, clock and reset                          ////
////  Versatile library, clock and reset                          ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Logic related to clock and reset                            ////
////  Logic related to clock and reset                            ////
////                                                              ////
////                                                              ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add more different registers                             ////
////   - add more different registers                             ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// Global buffer
// Global buffer
// usage:
// usage:
// use to enable global buffers for high fan out signals such as clock and reset
// use to enable global buffers for high fan out signals such as clock and reset
 
 
`ifdef ACTEL
`ifdef ACTEL
 
 
`timescale 1 ns/100 ps
`timescale 1 ns/100 ps
// Version: 8.4 8.4.0.33
// Version: 8.4 8.4.0.33
module gbuf(GL,CLK);
module gbuf(GL,CLK);
output GL;
output GL;
input  CLK;
input  CLK;
 
 
    wire GND;
    wire GND;
 
 
    GND GND_1_net(.Y(GND));
    GND GND_1_net(.Y(GND));
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
 
 
endmodule
endmodule
`timescale 1 ns/1 ns
`timescale 1 ns/1 ns
module vl_gbuf ( i, o);
module vl_gbuf ( i, o);
input i;
input i;
output o;
output o;
`ifdef SIM_GBUF
`ifdef SIM_GBUF
assign o=i;
assign o=i;
`else
`else
gbuf gbuf_i0 ( .CLK(i), .GL(o));
gbuf gbuf_i0 ( .CLK(i), .GL(o));
`endif
`endif
endmodule
endmodule
 
 
`else
`else
 
 
`ifdef ALTERA
`ifdef ALTERA
//altera
//altera
module vl_gbuf ( i, o);
module vl_gbuf ( i, o);
input i;
input i;
output o;
output o;
assign o = i;
assign o = i;
endmodule
endmodule
 
 
`else
`else
 
 
`timescale 1 ns/100 ps
`timescale 1 ns/100 ps
module vl_gbuf ( i, o);
module vl_gbuf ( i, o);
input i;
input i;
output o;
output o;
assign o = i;
assign o = i;
endmodule
endmodule
`endif // ALTERA
`endif // ALTERA
`endif //ACTEL
`endif //ACTEL
 
 
// sync reset
// sync reset
// input active lo async reset, normally from external reset generator and/or switch
// input active lo async reset, normally from external reset generator and/or switch
// output active high global reset sync with two DFFs 
// output active high global reset sync with two DFFs 
`timescale 1 ns/100 ps
`timescale 1 ns/100 ps
module vl_sync_rst ( rst_n_i, rst_o, clk);
module vl_sync_rst ( rst_n_i, rst_o, clk);
input rst_n_i, clk;
input rst_n_i, clk;
output rst_o;
output rst_o;
reg [1:0] tmp;
reg [1:0] tmp;
always @ (posedge clk or negedge rst_n_i)
always @ (posedge clk or negedge rst_n_i)
if (!rst_n_i)
if (!rst_n_i)
        tmp <= 2'b11;
        tmp <= 2'b11;
else
else
        tmp <= {1'b0,tmp[1]};
        tmp <= {1'b0,tmp[1]};
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
endmodule
endmodule
 
 
// vl_pll
// vl_pll
`ifdef ACTEL
`ifdef ACTEL
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
`timescale 1 ps/1 ps
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
parameter index = 0;
parameter index = 0;
parameter number_of_clk = 1;
parameter number_of_clk = 1;
parameter period_time_0 = 20000;
parameter period_time_0 = 20000;
parameter period_time_1 = 20000;
parameter period_time_1 = 20000;
parameter period_time_2 = 20000;
parameter period_time_2 = 20000;
parameter lock_delay = 2000000;
parameter lock_delay = 2000000;
input clk_i, rst_n_i;
input clk_i, rst_n_i;
output lock;
output lock;
output reg [0:number_of_clk-1] clk_o;
output reg [0:number_of_clk-1] clk_o;
output [0:number_of_clk-1] rst_o;
output [0:number_of_clk-1] rst_o;
 
 
`ifdef SIM_PLL
`ifdef SIM_PLL
 
 
always
always
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
 
 
generate if (number_of_clk > 1)
generate if (number_of_clk > 1)
always
always
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
endgenerate
endgenerate
 
 
generate if (number_of_clk > 2)
generate if (number_of_clk > 2)
always
always
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
endgenerate
endgenerate
 
 
genvar i;
genvar i;
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
end
end
endgenerate
endgenerate
 
 
assign #lock_delay lock = rst_n_i;
assign #lock_delay lock = rst_n_i;
 
 
endmodule
endmodule
`else
`else
generate if (number_of_clk==1 & index==0) begin
generate if (number_of_clk==1 & index==0) begin
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
end
end
endgenerate // index==0
endgenerate // index==0
generate if (number_of_clk==1 & index==1) begin
generate if (number_of_clk==1 & index==1) begin
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
end
end
endgenerate // index==1
endgenerate // index==1
generate if (number_of_clk==1 & index==2) begin
generate if (number_of_clk==1 & index==2) begin
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
end
end
endgenerate // index==2
endgenerate // index==2
generate if (number_of_clk==1 & index==3) begin
generate if (number_of_clk==1 & index==3) begin
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
end
end
endgenerate // index==0
endgenerate // index==0
 
 
generate if (number_of_clk==2 & index==0) begin
generate if (number_of_clk==2 & index==0) begin
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
end
end
endgenerate // index==0
endgenerate // index==0
generate if (number_of_clk==2 & index==1) begin
generate if (number_of_clk==2 & index==1) begin
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
end
end
endgenerate // index==1
endgenerate // index==1
generate if (number_of_clk==2 & index==2) begin
generate if (number_of_clk==2 & index==2) begin
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
end
end
endgenerate // index==2
endgenerate // index==2
generate if (number_of_clk==2 & index==3) begin
generate if (number_of_clk==2 & index==3) begin
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
end
end
endgenerate // index==0
endgenerate // index==0
 
 
generate if (number_of_clk==3 & index==0) begin
generate if (number_of_clk==3 & index==0) begin
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
end
end
endgenerate // index==0
endgenerate // index==0
generate if (number_of_clk==3 & index==1) begin
generate if (number_of_clk==3 & index==1) begin
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
end
end
endgenerate // index==1
endgenerate // index==1
generate if (number_of_clk==3 & index==2) begin
generate if (number_of_clk==3 & index==2) begin
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
end
end
endgenerate // index==2
endgenerate // index==2
generate if (number_of_clk==3 & index==3) begin
generate if (number_of_clk==3 & index==3) begin
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
end
end
endgenerate // index==0
endgenerate // index==0
 
 
genvar i;
genvar i;
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
end
end
endgenerate
endgenerate
endmodule
endmodule
`endif
`endif
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
 
 
`else
`else
 
 
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`ifdef ALTERA
`ifdef ALTERA
 
 
`timescale 1 ps/1 ps
`timescale 1 ps/1 ps
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
parameter index = 0;
parameter index = 0;
parameter number_of_clk = 1;
parameter number_of_clk = 1;
parameter period_time_0 = 20000;
parameter period_time_0 = 20000;
parameter period_time_1 = 20000;
parameter period_time_1 = 20000;
parameter period_time_2 = 20000;
parameter period_time_2 = 20000;
parameter period_time_3 = 20000;
parameter period_time_3 = 20000;
parameter period_time_4 = 20000;
parameter period_time_4 = 20000;
parameter lock_delay = 2000000;
parameter lock_delay = 2000000;
input clk_i, rst_n_i;
input clk_i, rst_n_i;
output lock;
output lock;
output reg [0:number_of_clk-1] clk_o;
output reg [0:number_of_clk-1] clk_o;
output [0:number_of_clk-1] rst_o;
output [0:number_of_clk-1] rst_o;
 
 
`ifdef SIM_PLL
`ifdef SIM_PLL
 
 
always
always
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
 
 
generate if (number_of_clk > 1)
generate if (number_of_clk > 1)
always
always
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
endgenerate
endgenerate
 
 
generate if (number_of_clk > 2)
generate if (number_of_clk > 2)
always
always
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
endgenerate
endgenerate
 
 
generate if (number_of_clk > 3)
generate if (number_of_clk > 3)
always
always
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
endgenerate
endgenerate
 
 
generate if (number_of_clk > 4)
generate if (number_of_clk > 4)
always
always
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
endgenerate
endgenerate
 
 
genvar i;
genvar i;
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
end
end
endgenerate
endgenerate
 
 
//assign #lock_delay lock = rst_n_i;
//assign #lock_delay lock = rst_n_i;
assign lock = rst_n_i;
assign lock = rst_n_i;
 
 
endmodule
endmodule
`else
`else
 
 
`ifdef VL_PLL0
`ifdef VL_PLL0
`ifdef VL_PLL0_CLK1
`ifdef VL_PLL0_CLK1
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
`endif
`endif
`ifdef VL_PLL0_CLK2
`ifdef VL_PLL0_CLK2
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
`endif
`endif
`ifdef VL_PLL0_CLK3
`ifdef VL_PLL0_CLK3
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
`endif
`endif
`ifdef VL_PLL0_CLK4
`ifdef VL_PLL0_CLK4
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
`endif
`endif
`ifdef VL_PLL0_CLK5
`ifdef VL_PLL0_CLK5
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
`endif
`endif
`endif
`endif
 
 
`ifdef VL_PLL1
`ifdef VL_PLL1
`ifdef VL_PLL1_CLK1
`ifdef VL_PLL1_CLK1
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
`endif
`endif
`ifdef VL_PLL1_CLK2
`ifdef VL_PLL1_CLK2
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
`endif
`endif
`ifdef VL_PLL1_CLK3
`ifdef VL_PLL1_CLK3
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
`endif
`endif
`ifdef VL_PLL1_CLK4
`ifdef VL_PLL1_CLK4
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
`endif
`endif
`ifdef VL_PLL1_CLK5
`ifdef VL_PLL1_CLK5
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
`endif
`endif
`endif
`endif
 
 
`ifdef VL_PLL2
`ifdef VL_PLL2
`ifdef VL_PLL2_CLK1
`ifdef VL_PLL2_CLK1
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
`endif
`endif
`ifdef VL_PLL2_CLK2
`ifdef VL_PLL2_CLK2
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
`endif
`endif
`ifdef VL_PLL2_CLK3
`ifdef VL_PLL2_CLK3
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
`endif
`endif
`ifdef VL_PLL2_CLK4
`ifdef VL_PLL2_CLK4
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
`endif
`endif
`ifdef VL_PLL2_CLK5
`ifdef VL_PLL2_CLK5
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
`endif
`endif
`endif
`endif
 
 
`ifdef VL_PLL3
`ifdef VL_PLL3
`ifdef VL_PLL3_CLK1
`ifdef VL_PLL3_CLK1
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
`endif
`endif
`ifdef VL_PLL3_CLK2
`ifdef VL_PLL3_CLK2
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
`endif
`endif
`ifdef VL_PLL3_CLK3
`ifdef VL_PLL3_CLK3
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
`endif
`endif
`ifdef VL_PLL3_CLK4
`ifdef VL_PLL3_CLK4
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
`endif
`endif
`ifdef VL_PLL3_CLK5
`ifdef VL_PLL3_CLK5
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
`endif
`endif
`endif
`endif
 
 
genvar i;
genvar i;
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
end
end
endgenerate
endgenerate
endmodule
endmodule
`endif
`endif
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
 
 
`else
`else
 
 
// generic PLL
// generic PLL
`timescale 1 ps/1 ps
`timescale 1 ps/1 ps
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
parameter index = 0;
parameter index = 0;
parameter number_of_clk = 1;
parameter number_of_clk = 1;
parameter period_time_0 = 20000;
parameter period_time_0 = 20000;
parameter period_time_1 = 20000;
parameter period_time_1 = 20000;
parameter period_time_2 = 20000;
parameter period_time_2 = 20000;
parameter lock_delay = 2000;
parameter lock_delay = 2000;
input clk_i, rst_n_i;
input clk_i, rst_n_i;
output lock;
output lock;
output reg [0:number_of_clk-1] clk_o;
output reg [0:number_of_clk-1] clk_o;
output [0:number_of_clk-1] rst_o;
output [0:number_of_clk-1] rst_o;
 
 
always
always
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
 
 
generate if (number_of_clk > 1)
generate if (number_of_clk > 1)
always
always
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
endgenerate
endgenerate
 
 
generate if (number_of_clk > 2)
generate if (number_of_clk > 2)
always
always
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
endgenerate
endgenerate
 
 
genvar i;
genvar i;
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
end
end
endgenerate
endgenerate
 
 
assign #lock_delay lock = rst_n_i;
assign #lock_delay lock = rst_n_i;
 
 
endmodule
endmodule
 
 
`endif //altera
`endif //altera
`endif //actel
`endif //actel
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile library, registers                                ////
////  Versatile library, registers                                ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Different type of registers                                 ////
////  Different type of registers                                 ////
////                                                              ////
////                                                              ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add more different registers                             ////
////   - add more different registers                             ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
module vl_dff ( d, q, clk, rst);
module vl_dff ( d, q, clk, rst);
 
 
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = 0;
 
 
        input [width-1:0] d;
        input [width-1:0] d;
        input clk, rst;
        input clk, rst;
        output reg [width-1:0] q;
        output reg [width-1:0] q;
 
 
        always @ (posedge clk or posedge rst)
        always @ (posedge clk or posedge rst)
        if (rst)
        if (rst)
                q <= reset_value;
                q <= reset_value;
        else
        else
                q <= d;
                q <= d;
 
 
endmodule
endmodule
 
 
module vl_dff_array ( d, q, clk, rst);
module vl_dff_array ( d, q, clk, rst);
 
 
        parameter width = 1;
        parameter width = 1;
        parameter depth = 2;
        parameter depth = 2;
        parameter reset_value = 1'b0;
        parameter reset_value = 1'b0;
 
 
        input [width-1:0] d;
        input [width-1:0] d;
        input clk, rst;
        input clk, rst;
        output [width-1:0] q;
        output [width-1:0] q;
        reg  [0:depth-1] q_tmp [width-1:0];
        reg  [0:depth-1] q_tmp [width-1:0];
        integer i;
        integer i;
        always @ (posedge clk or posedge rst)
        always @ (posedge clk or posedge rst)
        if (rst) begin
        if (rst) begin
            for (i=0;i<depth;i=i+1)
            for (i=0;i<depth;i=i+1)
                q_tmp[i] <= {width{reset_value}};
                q_tmp[i] <= {width{reset_value}};
        end else begin
        end else begin
            q_tmp[0] <= d;
            q_tmp[0] <= d;
            for (i=1;i<depth;i=i+1)
            for (i=1;i<depth;i=i+1)
                q_tmp[i] <= q_tmp[i-1];
                q_tmp[i] <= q_tmp[i-1];
        end
        end
 
 
    assign q = q_tmp[depth-1];
    assign q = q_tmp[depth-1];
 
 
endmodule
endmodule
 
 
module vl_dff_ce ( d, ce, q, clk, rst);
module vl_dff_ce ( d, ce, q, clk, rst);
 
 
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = 0;
 
 
        input [width-1:0] d;
        input [width-1:0] d;
        input ce, clk, rst;
        input ce, clk, rst;
        output reg [width-1:0] q;
        output reg [width-1:0] q;
 
 
        always @ (posedge clk or posedge rst)
        always @ (posedge clk or posedge rst)
        if (rst)
        if (rst)
                q <= reset_value;
                q <= reset_value;
        else
        else
                if (ce)
                if (ce)
                        q <= d;
                        q <= d;
 
 
endmodule
endmodule
 
 
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
 
 
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = 0;
 
 
        input [width-1:0] d;
        input [width-1:0] d;
        input ce, clear, clk, rst;
        input ce, clear, clk, rst;
        output reg [width-1:0] q;
        output reg [width-1:0] q;
 
 
        always @ (posedge clk or posedge rst)
        always @ (posedge clk or posedge rst)
        if (rst)
        if (rst)
            q <= reset_value;
            q <= reset_value;
        else
        else
            if (ce)
            if (ce)
                if (clear)
                if (clear)
                    q <= {width{1'b0}};
                    q <= {width{1'b0}};
                else
                else
                    q <= d;
                    q <= d;
 
 
endmodule
endmodule
 
 
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
 
 
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = 0;
 
 
        input [width-1:0] d;
        input [width-1:0] d;
        input ce, set, clk, rst;
        input ce, set, clk, rst;
        output reg [width-1:0] q;
        output reg [width-1:0] q;
 
 
        always @ (posedge clk or posedge rst)
        always @ (posedge clk or posedge rst)
        if (rst)
        if (rst)
            q <= reset_value;
            q <= reset_value;
        else
        else
            if (ce)
            if (ce)
                if (set)
                if (set)
                    q <= {width{1'b1}};
                    q <= {width{1'b1}};
                else
                else
                    q <= d;
                    q <= d;
 
 
endmodule
endmodule
 
 
module vl_spr ( sp, r, q, clk, rst);
module vl_spr ( sp, r, q, clk, rst);
 
 
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = 0;
 
 
        input sp, r;
        input sp, r;
        output reg q;
        output reg q;
        input clk, rst;
        input clk, rst;
 
 
        always @ (posedge clk or posedge rst)
        always @ (posedge clk or posedge rst)
        if (rst)
        if (rst)
            q <= reset_value;
            q <= reset_value;
        else
        else
            if (sp)
            if (sp)
                q <= 1'b1;
                q <= 1'b1;
            else if (r)
            else if (r)
                q <= 1'b0;
                q <= 1'b0;
 
 
endmodule
endmodule
 
 
module vl_srp ( s, rp, q, clk, rst);
module vl_srp ( s, rp, q, clk, rst);
 
 
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = 0;
 
 
        input s, rp;
        input s, rp;
        output reg q;
        output reg q;
        input clk, rst;
        input clk, rst;
 
 
        always @ (posedge clk or posedge rst)
        always @ (posedge clk or posedge rst)
        if (rst)
        if (rst)
            q <= reset_value;
            q <= reset_value;
        else
        else
            if (rp)
            if (rp)
                q <= 1'b0;
                q <= 1'b0;
            else if (s)
            else if (s)
                q <= 1'b1;
                q <= 1'b1;
 
 
endmodule
endmodule
 
 
 
 
`ifdef ALTERA
`ifdef ALTERA
// megafunction wizard: %LPM_FF%
// megafunction wizard: %LPM_FF%
// GENERATION: STANDARD
// GENERATION: STANDARD
// VERSION: WM1.0
// VERSION: WM1.0
// MODULE: lpm_ff 
// MODULE: lpm_ff 
 
 
// ============================================================
// ============================================================
// File Name: dff_sr.v
// File Name: dff_sr.v
// Megafunction Name(s):
// Megafunction Name(s):
//                      lpm_ff
//                      lpm_ff
//
//
// Simulation Library Files(s):
// Simulation Library Files(s):
//                      lpm
//                      lpm
// ============================================================
// ============================================================
// ************************************************************
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
//
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
// ************************************************************
// ************************************************************
 
 
 
 
//Copyright (C) 1991-2010 Altera Corporation
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions 
//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files from any of the foregoing 
//functions, and any output files from any of the foregoing 
//(including device programming or simulation files), and any 
//(including device programming or simulation files), and any 
//associated documentation or information are expressly subject 
//associated documentation or information are expressly subject 
//to the terms and conditions of the Altera Program License 
//to the terms and conditions of the Altera Program License 
//Subscription Agreement, Altera MegaCore Function License 
//Subscription Agreement, Altera MegaCore Function License 
//Agreement, or other applicable license agreement, including, 
//Agreement, or other applicable license agreement, including, 
//without limitation, that your use is for the sole purpose of 
//without limitation, that your use is for the sole purpose of 
//programming logic devices manufactured by Altera and sold by 
//programming logic devices manufactured by Altera and sold by 
//Altera or its authorized distributors.  Please refer to the 
//Altera or its authorized distributors.  Please refer to the 
//applicable agreement for further details.
//applicable agreement for further details.
 
 
 
 
// synopsys translate_off
// synopsys translate_off
`timescale 1 ps / 1 ps
`timescale 1 ps / 1 ps
// synopsys translate_on
// synopsys translate_on
module vl_dff_sr (
module vl_dff_sr (
        aclr,
        aclr,
        aset,
        aset,
        clock,
        clock,
        data,
        data,
        q);
        q);
 
 
        input     aclr;
        input     aclr;
        input     aset;
        input     aset;
        input     clock;
        input     clock;
        input     data;
        input     data;
        output    q;
        output    q;
 
 
        wire [0:0] sub_wire0;
        wire [0:0] sub_wire0;
        wire [0:0] sub_wire1 = sub_wire0[0:0];
        wire [0:0] sub_wire1 = sub_wire0[0:0];
        wire  q = sub_wire1;
        wire  q = sub_wire1;
        wire  sub_wire2 = data;
        wire  sub_wire2 = data;
        wire  sub_wire3 = sub_wire2;
        wire  sub_wire3 = sub_wire2;
 
 
        lpm_ff  lpm_ff_component (
        lpm_ff  lpm_ff_component (
                                .aclr (aclr),
                                .aclr (aclr),
                                .clock (clock),
                                .clock (clock),
                                .data (sub_wire3),
                                .data (sub_wire3),
                                .aset (aset),
                                .aset (aset),
                                .q (sub_wire0)
                                .q (sub_wire0)
                                // synopsys translate_off
                                // synopsys translate_off
                                ,
                                ,
                                .aload (),
                                .aload (),
                                .enable (),
                                .enable (),
                                .sclr (),
                                .sclr (),
                                .sload (),
                                .sload (),
                                .sset ()
                                .sset ()
                                // synopsys translate_on
                                // synopsys translate_on
                                );
                                );
        defparam
        defparam
                lpm_ff_component.lpm_fftype = "DFF",
                lpm_ff_component.lpm_fftype = "DFF",
                lpm_ff_component.lpm_type = "LPM_FF",
                lpm_ff_component.lpm_type = "LPM_FF",
                lpm_ff_component.lpm_width = 1;
                lpm_ff_component.lpm_width = 1;
 
 
 
 
endmodule
endmodule
 
 
// ============================================================
// ============================================================
// CNX file retrieval info
// CNX file retrieval info
// ============================================================
// ============================================================
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
// Retrieval info: PRIVATE: ASET NUMERIC "1"
// Retrieval info: PRIVATE: ASET NUMERIC "1"
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
// Retrieval info: PRIVATE: DFF NUMERIC "1"
// Retrieval info: PRIVATE: DFF NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: SSET NUMERIC "0"
// Retrieval info: PRIVATE: SSET NUMERIC "0"
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
// Retrieval info: PRIVATE: nBit NUMERIC "1"
// Retrieval info: PRIVATE: nBit NUMERIC "1"
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
// Retrieval info: LIB_FILE: lpm
 
 
 
 
`else
`else
 
 
 
 
module vl_dff_sr ( aclr, aset, clock, data, q);
module vl_dff_sr ( aclr, aset, clock, data, q);
 
 
    input         aclr;
    input         aclr;
    input         aset;
    input         aset;
    input         clock;
    input         clock;
    input         data;
    input         data;
    output reg    q;
    output reg    q;
 
 
   always @ (posedge clock or posedge aclr or posedge aset)
   always @ (posedge clock or posedge aclr or posedge aset)
     if (aclr)
     if (aclr)
       q <= 1'b0;
       q <= 1'b0;
     else if (aset)
     else if (aset)
       q <= 1'b1;
       q <= 1'b1;
     else
     else
       q <= data;
       q <= data;
 
 
endmodule
endmodule
 
 
`endif
`endif
 
 
// LATCH
// LATCH
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
`ifdef ALTERA
`ifdef ALTERA
module vl_latch ( d, le, q, clk);
module vl_latch ( d, le, q, clk);
input d, le;
input d, le;
output q;
output q;
input clk;
input clk;
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
endmodule
endmodule
`else
`else
module latch ( d, le, q, clk);
module latch ( d, le, q, clk);
input d, le;
input d, le;
output q;
output q;
input clk;/*
input clk;/*
   always @ (posedge direction_set or posedge direction_clr)
   always @ (posedge direction_set or posedge direction_clr)
     if (direction_clr)
     if (direction_clr)
       direction <= going_empty;
       direction <= going_empty;
     else
     else
       direction <= going_full;*/
       direction <= going_full;*/
endmodule
endmodule
`endif
`endif
 
 
module vl_shreg ( d, q, clk, rst);
module vl_shreg ( d, q, clk, rst);
parameter depth = 10;
parameter depth = 10;
input d;
input d;
output q;
output q;
input clk, rst;
input clk, rst;
 
 
reg [1:depth] dffs;
reg [1:depth] dffs;
 
 
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
if (rst)
if (rst)
    dffs <= {depth{1'b0}};
    dffs <= {depth{1'b0}};
else
else
    dffs <= {d,dffs[1:depth-1]};
    dffs <= {d,dffs[1:depth-1]};
assign q = dffs[depth];
assign q = dffs[depth];
endmodule
endmodule
 
 
module vl_shreg_ce ( d, ce, q, clk, rst);
module vl_shreg_ce ( d, ce, q, clk, rst);
parameter depth = 10;
parameter depth = 10;
input d, ce;
input d, ce;
output q;
output q;
input clk, rst;
input clk, rst;
 
 
reg [1:depth] dffs;
reg [1:depth] dffs;
 
 
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
if (rst)
if (rst)
    dffs <= {depth{1'b0}};
    dffs <= {depth{1'b0}};
else
else
    if (ce)
    if (ce)
        dffs <= {d,dffs[1:depth-1]};
        dffs <= {d,dffs[1:depth-1]};
assign q = dffs[depth];
assign q = dffs[depth];
endmodule
endmodule
 
 
module vl_delay ( d, q, clk, rst);
module vl_delay ( d, q, clk, rst);
parameter depth = 10;
parameter depth = 10;
input d;
input d;
output q;
output q;
input clk, rst;
input clk, rst;
 
 
reg [1:depth] dffs;
reg [1:depth] dffs;
 
 
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
if (rst)
if (rst)
    dffs <= {depth{1'b0}};
    dffs <= {depth{1'b0}};
else
else
    dffs <= {d,dffs[1:depth-1]};
    dffs <= {d,dffs[1:depth-1]};
assign q = dffs[depth];
assign q = dffs[depth];
endmodule
endmodule
 
 
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
parameter depth = 10;
parameter depth = 10;
input d;
input d;
output q, emptyflag;
output q, emptyflag;
input clk, rst;
input clk, rst;
 
 
reg [1:depth] dffs;
reg [1:depth] dffs;
 
 
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
if (rst)
if (rst)
    dffs <= {depth{1'b0}};
    dffs <= {depth{1'b0}};
else
else
    dffs <= {d,dffs[1:depth-1]};
    dffs <= {d,dffs[1:depth-1]};
assign q = dffs[depth];
assign q = dffs[depth];
assign emptyflag = !(|dffs);
assign emptyflag = !(|dffs);
endmodule
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Logic functions                                             ////
////  Logic functions                                             ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Logic functions such as multiplexers                        ////
////  Logic functions such as multiplexers                        ////
////                                                              ////
////                                                              ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   -                                                          ////
////   -                                                          ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
module vl_mux2_andor ( a1, a0, sel, dout);
module vl_mux2_andor ( a1, a0, sel, dout);
 
 
parameter width = 32;
parameter width = 32;
parameter nr_of_ports = 2;
localparam nr_of_ports = 2;
input [width-1:0] a1, a0;
input [width-1:0] a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
output [width-1:0] dout;
 
 
wire [width-1:0] tmp [nr_of_ports-1:0];
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
integer i;
 
 
// and
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[1] = {width{sel[1]}} & a1;
 
 
// or
// or
assign dout = tmp[1] | tmp[0];
assign dout = tmp[1] | tmp[0];
 
 
endmodule
endmodule
 
 
module vl_mux3_andor ( a2, a1, a0, sel, dout);
module vl_mux3_andor ( a2, a1, a0, sel, dout);
 
 
parameter width = 32;
parameter width = 32;
parameter nr_of_ports = 3;
localparam nr_of_ports = 3;
input [width-1:0] a2, a1, a0;
input [width-1:0] a2, a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
output [width-1:0] dout;
 
 
wire [width-1:0] tmp [nr_of_ports-1:0];
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
integer i;
 
 
// and
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
assign tmp[2] = {width{sel[2]}} & a2;
 
 
// or
// or
assign dout = tmp[2] | tmp[1] | tmp[0];
assign dout = tmp[2] | tmp[1] | tmp[0];
 
 
endmodule
endmodule
 
 
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
 
 
parameter width = 32;
parameter width = 32;
parameter nr_of_ports = 4;
localparam nr_of_ports = 4;
input [width-1:0] a3, a2, a1, a0;
input [width-1:0] a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
output [width-1:0] dout;
 
 
wire [width-1:0] tmp [nr_of_ports-1:0];
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
integer i;
 
 
// and
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
assign tmp[2] = {width{sel[2]}} & a2;
assign tmp[3] = {width{sel[3]}} & a3;
assign tmp[3] = {width{sel[3]}} & a3;
 
 
// or
// or
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
 
 
endmodule
endmodule
 
 
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
 
 
parameter width = 32;
parameter width = 32;
parameter nr_of_ports = 5;
localparam nr_of_ports = 5;
input [width-1:0] a4, a3, a2, a1, a0;
input [width-1:0] a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
output [width-1:0] dout;
 
 
wire [width-1:0] tmp [nr_of_ports-1:0];
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
integer i;
 
 
// and
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
assign tmp[2] = {width{sel[2]}} & a2;
assign tmp[3] = {width{sel[3]}} & a3;
assign tmp[3] = {width{sel[3]}} & a3;
assign tmp[4] = {width{sel[4]}} & a4;
assign tmp[4] = {width{sel[4]}} & a4;
 
 
// or
// or
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
 
 
endmodule
endmodule
 
 
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
 
 
parameter width = 32;
parameter width = 32;
parameter nr_of_ports = 6;
localparam nr_of_ports = 6;
input [width-1:0] a5, a4, a3, a2, a1, a0;
input [width-1:0] a5, a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
output [width-1:0] dout;
 
 
wire [width-1:0] tmp [nr_of_ports-1:0];
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
integer i;
 
 
// and
// and
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[1] = {width{sel[1]}} & a1;
assign tmp[2] = {width{sel[2]}} & a2;
assign tmp[2] = {width{sel[2]}} & a2;
assign tmp[3] = {width{sel[3]}} & a3;
assign tmp[3] = {width{sel[3]}} & a3;
assign tmp[4] = {width{sel[4]}} & a4;
assign tmp[4] = {width{sel[4]}} & a4;
assign tmp[5] = {width{sel[5]}} & a5;
assign tmp[5] = {width{sel[5]}} & a5;
 
 
// or
// or
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
 
 
endmodule
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////  counter                                                     ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// binary counter
// binary counter
module vl_cnt_bin ( q, rst, clk);
module vl_cnt_bin ( q, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   output [length:1] q;
   output [length:1] q;
   input rst;
   input rst;
   input clk;
   input clk;
 
 
   parameter clear_value = 0;
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter set_value = 1;
   parameter wrap_value = 0;
   parameter wrap_value = 0;
   parameter level1_value = 15;
   parameter level1_value = 15;
 
 
   reg  [length:1] qi;
   reg  [length:1] qi;
   wire [length:1] q_next;
   wire [length:1] q_next;
   assign q_next = qi + {{length-1{1'b0}},1'b1};
   assign q_next = qi + {{length-1{1'b0}},1'b1};
 
 
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       qi <= {length{1'b0}};
       qi <= {length{1'b0}};
     else
     else
       qi <= q_next;
       qi <= q_next;
 
 
   assign q = qi;
   assign q = qi;
 
 
endmodule
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////  counter                                                     ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// binary counter
// binary counter
module vl_cnt_bin_clear ( clear, q, rst, clk);
module vl_cnt_bin_clear ( clear, q, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   input clear;
   input clear;
   output [length:1] q;
   output [length:1] q;
   input rst;
   input rst;
   input clk;
   input clk;
 
 
   parameter clear_value = 0;
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter set_value = 1;
   parameter wrap_value = 0;
   parameter wrap_value = 0;
   parameter level1_value = 15;
   parameter level1_value = 15;
 
 
   reg  [length:1] qi;
   reg  [length:1] qi;
   wire [length:1] q_next;
   wire [length:1] q_next;
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
 
 
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       qi <= {length{1'b0}};
       qi <= {length{1'b0}};
     else
     else
       qi <= q_next;
       qi <= q_next;
 
 
   assign q = qi;
   assign q = qi;
 
 
endmodule
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////  counter                                                     ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// binary counter
// binary counter
module vl_cnt_bin_ce ( cke, q, rst, clk);
module vl_cnt_bin_ce ( cke, q, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   output [length:1] q;
   output [length:1] q;
   input rst;
   input rst;
   input clk;
   input clk;
 
 
   parameter clear_value = 0;
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter set_value = 1;
   parameter wrap_value = 0;
   parameter wrap_value = 0;
   parameter level1_value = 15;
   parameter level1_value = 15;
 
 
   reg  [length:1] qi;
   reg  [length:1] qi;
   wire [length:1] q_next;
   wire [length:1] q_next;
   assign q_next = qi + {{length-1{1'b0}},1'b1};
   assign q_next = qi + {{length-1{1'b0}},1'b1};
 
 
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       qi <= {length{1'b0}};
       qi <= {length{1'b0}};
     else
     else
     if (cke)
     if (cke)
       qi <= q_next;
       qi <= q_next;
 
 
   assign q = qi;
   assign q = qi;
 
 
endmodule
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////  counter                                                     ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// binary counter
// binary counter
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   input clear;
   input clear;
   input cke;
   input cke;
   output [length:1] q;
   output [length:1] q;
   input rst;
   input rst;
   input clk;
   input clk;
 
 
   parameter clear_value = 0;
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter set_value = 1;
   parameter wrap_value = 0;
   parameter wrap_value = 0;
   parameter level1_value = 15;
   parameter level1_value = 15;
 
 
   reg  [length:1] qi;
   reg  [length:1] qi;
   wire [length:1] q_next;
   wire [length:1] q_next;
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
 
 
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       qi <= {length{1'b0}};
       qi <= {length{1'b0}};
     else
     else
     if (cke)
     if (cke)
       qi <= q_next;
       qi <= q_next;
 
 
   assign q = qi;
   assign q = qi;
 
 
endmodule
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////  counter                                                     ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// binary counter
// binary counter
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk);
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   input clear;
   input clear;
   input cke;
   input cke;
   output [length:1] q;
   output [length:1] q;
   output reg level1;
   output reg level1;
   output reg level2;
   output reg level2;
   input rst;
   input rst;
   input clk;
   input clk;
 
 
   parameter clear_value = 0;
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter set_value = 1;
   parameter wrap_value = 15;
   parameter wrap_value = 15;
   parameter level1_value = 8;
   parameter level1_value = 8;
   parameter level2_value = 15;
   parameter level2_value = 15;
 
 
   wire rew;
   wire rew;
   assign rew = 1'b0;
   assign rew = 1'b0;
   reg  [length:1] qi;
   reg  [length:1] qi;
   wire [length:1] q_next;
   wire [length:1] q_next;
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
 
 
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       qi <= {length{1'b0}};
       qi <= {length{1'b0}};
     else
     else
     if (cke)
     if (cke)
       qi <= q_next;
       qi <= q_next;
 
 
   assign q = qi;
   assign q = qi;
 
 
 
 
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        level1 <= 1'b0;
        level1 <= 1'b0;
    else
    else
    if (cke)
    if (cke)
    if (clear)
    if (clear)
        level1 <= 1'b0;
        level1 <= 1'b0;
    else if (q_next == level1_value)
    else if (q_next == level1_value)
        level1 <= 1'b1;
        level1 <= 1'b1;
    else if (qi == level1_value & rew)
    else if (qi == level1_value & rew)
        level1 <= 1'b0;
        level1 <= 1'b0;
 
 
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        level2 <= 1'b0;
        level2 <= 1'b0;
    else
    else
    if (cke)
    if (cke)
    if (clear)
    if (clear)
        level2 <= 1'b0;
        level2 <= 1'b0;
    else if (q_next == level2_value)
    else if (q_next == level2_value)
        level2 <= 1'b1;
        level2 <= 1'b1;
    else if (qi == level2_value & rew)
    else if (qi == level2_value & rew)
        level2 <= 1'b0;
        level2 <= 1'b0;
endmodule
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////  counter                                                     ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// binary counter
// binary counter
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   input clear;
   input clear;
   input set;
   input set;
   input cke;
   input cke;
   input rew;
   input rew;
   output [length:1] q;
   output [length:1] q;
   input rst;
   input rst;
   input clk;
   input clk;
 
 
   parameter clear_value = 0;
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter set_value = 1;
   parameter wrap_value = 0;
   parameter wrap_value = 0;
   parameter level1_value = 15;
   parameter level1_value = 15;
 
 
   reg  [length:1] qi;
   reg  [length:1] qi;
   wire  [length:1] q_next, q_next_fw, q_next_rew;
   wire  [length:1] q_next, q_next_fw, q_next_rew;
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
   assign q_next = rew ? q_next_rew : q_next_fw;
   assign q_next = rew ? q_next_rew : q_next_fw;
 
 
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       qi <= {length{1'b0}};
       qi <= {length{1'b0}};
     else
     else
     if (cke)
     if (cke)
       qi <= q_next;
       qi <= q_next;
 
 
   assign q = qi;
   assign q = qi;
 
 
endmodule
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////  counter                                                     ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// binary counter
// binary counter
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   input rew;
   input rew;
   output reg level1;
   output reg level1;
   input rst;
   input rst;
   input clk;
   input clk;
 
 
   parameter clear_value = 0;
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter set_value = 1;
   parameter wrap_value = 1;
   parameter wrap_value = 1;
   parameter level1_value = 15;
   parameter level1_value = 15;
 
 
   wire clear;
   wire clear;
   assign clear = 1'b0;
   assign clear = 1'b0;
   reg  [length:1] qi;
   reg  [length:1] qi;
   wire  [length:1] q_next, q_next_fw, q_next_rew;
   wire  [length:1] q_next, q_next_fw, q_next_rew;
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
   assign q_next = rew ? q_next_rew : q_next_fw;
   assign q_next = rew ? q_next_rew : q_next_fw;
 
 
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       qi <= {length{1'b0}};
       qi <= {length{1'b0}};
     else
     else
     if (cke)
     if (cke)
       qi <= q_next;
       qi <= q_next;
 
 
 
 
 
 
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        level1 <= 1'b0;
        level1 <= 1'b0;
    else
    else
    if (cke)
    if (cke)
    if (clear)
    if (clear)
        level1 <= 1'b0;
        level1 <= 1'b0;
    else if (q_next == level1_value)
    else if (q_next == level1_value)
        level1 <= 1'b1;
        level1 <= 1'b1;
    else if (qi == level1_value & rew)
    else if (qi == level1_value & rew)
        level1 <= 1'b0;
        level1 <= 1'b0;
endmodule
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////  counter                                                     ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// binary counter
// binary counter
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk);
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   input rew;
   input rew;
   output reg zq;
   output reg zq;
   output reg level1;
   output reg level1;
   input rst;
   input rst;
   input clk;
   input clk;
 
 
   parameter clear_value = 0;
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter set_value = 1;
   parameter wrap_value = 1;
   parameter wrap_value = 1;
   parameter level1_value = 15;
   parameter level1_value = 15;
 
 
   wire clear;
   wire clear;
   assign clear = 1'b0;
   assign clear = 1'b0;
   reg  [length:1] qi;
   reg  [length:1] qi;
   wire  [length:1] q_next, q_next_fw, q_next_rew;
   wire  [length:1] q_next, q_next_fw, q_next_rew;
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
   assign q_next = rew ? q_next_rew : q_next_fw;
   assign q_next = rew ? q_next_rew : q_next_fw;
 
 
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       qi <= {length{1'b0}};
       qi <= {length{1'b0}};
     else
     else
     if (cke)
     if (cke)
       qi <= q_next;
       qi <= q_next;
 
 
 
 
 
 
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       zq <= 1'b1;
       zq <= 1'b1;
     else
     else
     if (cke)
     if (cke)
       zq <= q_next == {length{1'b0}};
       zq <= q_next == {length{1'b0}};
 
 
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        level1 <= 1'b0;
        level1 <= 1'b0;
    else
    else
    if (cke)
    if (cke)
    if (clear)
    if (clear)
        level1 <= 1'b0;
        level1 <= 1'b0;
    else if (q_next == level1_value)
    else if (q_next == level1_value)
        level1 <= 1'b1;
        level1 <= 1'b1;
    else if (qi == level1_value & rew)
    else if (qi == level1_value & rew)
        level1 <= 1'b0;
        level1 <= 1'b0;
endmodule
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////  counter                                                     ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// binary counter
// binary counter
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk);
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   input rew;
   input rew;
   output [length:1] q;
   output [length:1] q;
   output reg zq;
   output reg zq;
   output reg level1;
   output reg level1;
   input rst;
   input rst;
   input clk;
   input clk;
 
 
   parameter clear_value = 0;
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter set_value = 1;
   parameter wrap_value = 1;
   parameter wrap_value = 1;
   parameter level1_value = 15;
   parameter level1_value = 15;
 
 
   wire clear;
   wire clear;
   assign clear = 1'b0;
   assign clear = 1'b0;
   reg  [length:1] qi;
   reg  [length:1] qi;
   wire  [length:1] q_next, q_next_fw, q_next_rew;
   wire  [length:1] q_next, q_next_fw, q_next_rew;
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
   assign q_next = rew ? q_next_rew : q_next_fw;
   assign q_next = rew ? q_next_rew : q_next_fw;
 
 
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       qi <= {length{1'b0}};
       qi <= {length{1'b0}};
     else
     else
     if (cke)
     if (cke)
       qi <= q_next;
       qi <= q_next;
 
 
   assign q = qi;
   assign q = qi;
 
 
 
 
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       zq <= 1'b1;
       zq <= 1'b1;
     else
     else
     if (cke)
     if (cke)
       zq <= q_next == {length{1'b0}};
       zq <= q_next == {length{1'b0}};
 
 
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        level1 <= 1'b0;
        level1 <= 1'b0;
    else
    else
    if (cke)
    if (cke)
    if (clear)
    if (clear)
        level1 <= 1'b0;
        level1 <= 1'b0;
    else if (q_next == level1_value)
    else if (q_next == level1_value)
        level1 <= 1'b1;
        level1 <= 1'b1;
    else if (qi == level1_value & rew)
    else if (qi == level1_value & rew)
        level1 <= 1'b0;
        level1 <= 1'b0;
endmodule
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////  counter                                                     ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// LFSR counter
// LFSR counter
module vl_cnt_lfsr_zq ( zq, rst, clk);
module vl_cnt_lfsr_zq ( zq, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   output reg zq;
   output reg zq;
   input rst;
   input rst;
   input clk;
   input clk;
 
 
   parameter clear_value = 0;
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter set_value = 1;
   parameter wrap_value = 8;
   parameter wrap_value = 8;
   parameter level1_value = 15;
   parameter level1_value = 15;
 
 
   reg  [length:1] qi;
   reg  [length:1] qi;
   reg lfsr_fb;
   reg lfsr_fb;
   wire [length:1] q_next;
   wire [length:1] q_next;
   reg [32:1] polynom;
   reg [32:1] polynom;
   integer i;
   integer i;
 
 
   always @ (qi)
   always @ (qi)
   begin
   begin
        case (length)
        case (length)
         2: polynom = 32'b11;                               // 0x3
         2: polynom = 32'b11;                               // 0x3
         3: polynom = 32'b110;                              // 0x6
         3: polynom = 32'b110;                              // 0x6
         4: polynom = 32'b1100;                             // 0xC
         4: polynom = 32'b1100;                             // 0xC
         5: polynom = 32'b10100;                            // 0x14
         5: polynom = 32'b10100;                            // 0x14
         6: polynom = 32'b110000;                           // 0x30
         6: polynom = 32'b110000;                           // 0x30
         7: polynom = 32'b1100000;                          // 0x60
         7: polynom = 32'b1100000;                          // 0x60
         8: polynom = 32'b10111000;                         // 0xb8
         8: polynom = 32'b10111000;                         // 0xb8
         9: polynom = 32'b100010000;                        // 0x110
         9: polynom = 32'b100010000;                        // 0x110
        10: polynom = 32'b1001000000;                       // 0x240
        10: polynom = 32'b1001000000;                       // 0x240
        11: polynom = 32'b10100000000;                      // 0x500
        11: polynom = 32'b10100000000;                      // 0x500
        12: polynom = 32'b100000101001;                     // 0x829
        12: polynom = 32'b100000101001;                     // 0x829
        13: polynom = 32'b1000000001100;                    // 0x100C
        13: polynom = 32'b1000000001100;                    // 0x100C
        14: polynom = 32'b10000000010101;                   // 0x2015
        14: polynom = 32'b10000000010101;                   // 0x2015
        15: polynom = 32'b110000000000000;                  // 0x6000
        15: polynom = 32'b110000000000000;                  // 0x6000
        16: polynom = 32'b1101000000001000;                 // 0xD008
        16: polynom = 32'b1101000000001000;                 // 0xD008
        17: polynom = 32'b10010000000000000;                // 0x12000
        17: polynom = 32'b10010000000000000;                // 0x12000
        18: polynom = 32'b100000010000000000;               // 0x20400
        18: polynom = 32'b100000010000000000;               // 0x20400
        19: polynom = 32'b1000000000000100011;              // 0x40023
        19: polynom = 32'b1000000000000100011;              // 0x40023
        20: polynom = 32'b10000010000000000000;             // 0x82000
        20: polynom = 32'b10000010000000000000;             // 0x82000
        21: polynom = 32'b101000000000000000000;            // 0x140000
        21: polynom = 32'b101000000000000000000;            // 0x140000
        22: polynom = 32'b1100000000000000000000;           // 0x300000
        22: polynom = 32'b1100000000000000000000;           // 0x300000
        23: polynom = 32'b10000100000000000000000;          // 0x420000
        23: polynom = 32'b10000100000000000000000;          // 0x420000
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
        default: polynom = 32'b0;
        default: polynom = 32'b0;
        endcase
        endcase
        lfsr_fb = qi[length];
        lfsr_fb = qi[length];
        for (i=length-1; i>=1; i=i-1) begin
        for (i=length-1; i>=1; i=i-1) begin
            if (polynom[i])
            if (polynom[i])
                lfsr_fb = lfsr_fb  ~^ qi[i];
                lfsr_fb = lfsr_fb  ~^ qi[i];
        end
        end
    end
    end
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
 
 
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       qi <= {length{1'b0}};
       qi <= {length{1'b0}};
     else
     else
       qi <= q_next;
       qi <= q_next;
 
 
 
 
 
 
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       zq <= 1'b1;
       zq <= 1'b1;
     else
     else
       zq <= q_next == {length{1'b0}};
       zq <= q_next == {length{1'b0}};
endmodule
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////  counter                                                     ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// LFSR counter
// LFSR counter
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   output reg zq;
   output reg zq;
   input rst;
   input rst;
   input clk;
   input clk;
 
 
   parameter clear_value = 0;
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter set_value = 1;
   parameter wrap_value = 8;
   parameter wrap_value = 8;
   parameter level1_value = 15;
   parameter level1_value = 15;
 
 
   reg  [length:1] qi;
   reg  [length:1] qi;
   reg lfsr_fb;
   reg lfsr_fb;
   wire [length:1] q_next;
   wire [length:1] q_next;
   reg [32:1] polynom;
   reg [32:1] polynom;
   integer i;
   integer i;
 
 
   always @ (qi)
   always @ (qi)
   begin
   begin
        case (length)
        case (length)
         2: polynom = 32'b11;                               // 0x3
         2: polynom = 32'b11;                               // 0x3
         3: polynom = 32'b110;                              // 0x6
         3: polynom = 32'b110;                              // 0x6
         4: polynom = 32'b1100;                             // 0xC
         4: polynom = 32'b1100;                             // 0xC
         5: polynom = 32'b10100;                            // 0x14
         5: polynom = 32'b10100;                            // 0x14
         6: polynom = 32'b110000;                           // 0x30
         6: polynom = 32'b110000;                           // 0x30
         7: polynom = 32'b1100000;                          // 0x60
         7: polynom = 32'b1100000;                          // 0x60
         8: polynom = 32'b10111000;                         // 0xb8
         8: polynom = 32'b10111000;                         // 0xb8
         9: polynom = 32'b100010000;                        // 0x110
         9: polynom = 32'b100010000;                        // 0x110
        10: polynom = 32'b1001000000;                       // 0x240
        10: polynom = 32'b1001000000;                       // 0x240
        11: polynom = 32'b10100000000;                      // 0x500
        11: polynom = 32'b10100000000;                      // 0x500
        12: polynom = 32'b100000101001;                     // 0x829
        12: polynom = 32'b100000101001;                     // 0x829
        13: polynom = 32'b1000000001100;                    // 0x100C
        13: polynom = 32'b1000000001100;                    // 0x100C
        14: polynom = 32'b10000000010101;                   // 0x2015
        14: polynom = 32'b10000000010101;                   // 0x2015
        15: polynom = 32'b110000000000000;                  // 0x6000
        15: polynom = 32'b110000000000000;                  // 0x6000
        16: polynom = 32'b1101000000001000;                 // 0xD008
        16: polynom = 32'b1101000000001000;                 // 0xD008
        17: polynom = 32'b10010000000000000;                // 0x12000
        17: polynom = 32'b10010000000000000;                // 0x12000
        18: polynom = 32'b100000010000000000;               // 0x20400
        18: polynom = 32'b100000010000000000;               // 0x20400
        19: polynom = 32'b1000000000000100011;              // 0x40023
        19: polynom = 32'b1000000000000100011;              // 0x40023
        20: polynom = 32'b10000010000000000000;             // 0x82000
        20: polynom = 32'b10000010000000000000;             // 0x82000
        21: polynom = 32'b101000000000000000000;            // 0x140000
        21: polynom = 32'b101000000000000000000;            // 0x140000
        22: polynom = 32'b1100000000000000000000;           // 0x300000
        22: polynom = 32'b1100000000000000000000;           // 0x300000
        23: polynom = 32'b10000100000000000000000;          // 0x420000
        23: polynom = 32'b10000100000000000000000;          // 0x420000
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
        29: polynom = 3</