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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Diff between revs 39 and 40

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Line 1... Line 1...
 
`ifndef BASE
 
`define BASE vl_
 
`endif
 
 
 
`ifdef ALL
 
 
 
`define GBUF
 
`define SYNC_RST
 
`define PLL
 
 
 
`define MULTS
 
`define MULTS18X18
 
`define MULT
 
`define SHIFT_UNIT_32
 
`define LOGIC_UNIT
 
 
 
`define CNT_SHREG_WRAP
 
`define CNT_SHREG_CE_WRAP
 
`define CNT_SHREG_CE_CLEAR
 
`define CNT_SHREG_CE_CLEAR_WRAP
 
 
 
`define MUX_ANDOR
 
`define MUX2_ANDOR
 
`define MUX3_ANDOR
 
`define MUX4_ANDOR
 
`define MUX5_ANDOR
 
`define MUX6_ANDOR
 
 
 
`define ROM_INIT
 
`define RAM
 
`define RAM_BE
 
`define DPRAM_1R1W
 
`define DPRAM_2R1W
 
`define DPRAM_2R2W
 
`define FIFO_1R1W_FILL_LEVEL_SYNC
 
`define FIFO_2R2W_SYNC_SIMPLEX
 
`define FIFO_CMP_ASYNC
 
`define FIFO_1R1W_ASYNC
 
`define FIFO_2R2W_ASYNC
 
`define FIFO_2R2W_ASYNC_SIMPLEX
 
 
 
`define DFF
 
`define DFF_ARRAY
 
`define DFF_CE
 
`define DFF_CE_CLEAR
 
`define DF_CE_SET
 
`define SPR
 
`define SRP
 
`define DFF_SR
 
`define LATCH
 
`define SHREG
 
`define SHREG_CE
 
`define DELAY
 
`define DELAY_EMPTYFLAG
 
 
 
`define WB3WB3_BRIDGE
 
`define WB3_ARBITER_TYPE1
 
`define WB_BOOT_ROM
 
`define WB_DPRAM
 
 
 
`endif
 
 
 
`ifdef PLL
 
`ifndef SYNC_RST
 
`define SYNC_RST
 
`endif
 
`endif
 
 
 
`ifdef SYNC_RST
 
`ifndef GBUF
 
`define GBUF
 
`endif
 
`endif
 
 
 
`ifdef WB_DPRAM
 
`ifndef DPRAM_2R2W
 
`define DPRAM_2R2W
 
`endif
 
`ifndef SPR
 
`define SPR
 
`endif
 
`endif
 
 
 
`ifdef WB3_ARBITER_TYPE1
 
`ifndef MUX_ANDOR
 
`define MUX_ANDOR
 
`endif
 
`endif
 
 
 
`ifdef WB3WB3_BRIDGE
 
`ifndef CNT_SHREG_CE_CLEAR
 
`define CNT_SHREG_CE_CLEAR
 
`endif
 
`ifndef DFF
 
`define DFF
 
`endif
 
`ifndef DFF_CE
 
`define DFF_CE
 
`endif
 
`ifndef CNT_SHREG_CE_CLEAR
 
`define CNT_SHREG_CE_CLEAR
 
`endif
 
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
 
`define FIFO_2R2W_ASYNC_SIMPLEX
 
`endif
 
`endif
 
 
 
`ifdef MULTS18X18
 
`ifndef MULTS
 
`define MULTS
 
`endif
 
`endif
 
 
 
`ifdef SHIFT_UNIT_32
 
`ifndef MULTS
 
`define MULTS
 
`endif
 
`endif
 
 
 
`ifdef MUX2_ANDOR
 
`ifndef MUX_ANDOR
 
`define MUX_ANDOR
 
`endif
 
`endif
 
 
 
`ifdef MUX3_ANDOR
 
`ifndef MUX_ANDOR
 
`define MUX_ANDOR
 
`endif
 
`endif
 
 
 
`ifdef MUX4_ANDOR
 
`ifndef MUX_ANDOR
 
`define MUX_ANDOR
 
`endif
 
`endif
 
 
 
`ifdef MUX5_ANDOR
 
`ifndef MUX_ANDOR
 
`define MUX_ANDOR
 
`endif
 
`endif
 
 
 
`ifdef MUX6_ANDOR
 
`ifndef MUX_ANDOR
 
`define MUX_ANDOR
 
`endif
 
`endif
 
 
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
 
`ifndef CNT_BIN_CE
 
`define CNT_BIN_CE
 
`endif
 
`ifndef DPRAM_1R1W
 
`define DPRAM_1R1W
 
`endif
 
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
 
`define CNT_BIN_CE_REW_Q_ZQ_L1
 
`endif
 
`endif
 
 
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
 
`ifndef CNT_LFSR_CE
 
`define CNT_LFSR_CE
 
`endif
 
`ifndef DPRAM_2R2W
 
`define DPRAM_2R2W
 
`endif
 
`ifndef CNT_BIN_CE_REW_ZQ_L1
 
`define CNT_BIN_CE_REW_ZQ_L1
 
`endif
 
`endif
 
 
 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
 
`ifndef CNT_GRAY_CE_BIN
 
`define CNT_GRAY_CE_BIN
 
`endif
 
`ifndef DPRAM_2R2W
 
`define DPRAM_2R2W
 
`endif
 
`ifndef FIFO_CMP_ASYNC
 
`define FIFO_CMP_ASYNC
 
`endif
 
`endif
 
 
 
`ifdef FIFO_2R2W_ASYNC
 
`ifndef FIFO_1R1W_ASYNC
 
`define FIFO_1R1W_ASYNC
 
`endif
 
`endif
 
 
 
`ifdef FIFO_1R1W_ASYNC
 
`ifndef CNT_GRAY_CE_BIN
 
`define CNT_GRAY_CE_BIN
 
`endif
 
`ifndef DPRAM_1R1W
 
`define DPRAM_1R1W
 
`endif
 
`ifndef FIFO_CMP_ASYNC
 
`define FIFO_CMP_ASYNC
 
`endif
 
`endif
 
 
 
`ifdef FIFO_CMP_ASYNC
 
`ifndef DFF_SR
 
`define DFF_SR
 
`endif
 
`ifndef DFF
 
`define DFF
 
`endif
 
`endif
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile library, clock and reset                          ////
////  Versatile library, clock and reset                          ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
Line 43... Line 254...
// Global buffer
// Global buffer
// usage:
// usage:
// use to enable global buffers for high fan out signals such as clock and reset
// use to enable global buffers for high fan out signals such as clock and reset
 
 
`ifdef ACTEL
`ifdef ACTEL
 
`ifdef GBUF
`timescale 1 ns/100 ps
`timescale 1 ns/100 ps
// Version: 8.4 8.4.0.33
// Version: 8.4 8.4.0.33
module gbuf(GL,CLK);
module gbuf(GL,CLK);
output GL;
output GL;
input  CLK;
input  CLK;
Line 58... Line 269...
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
 
 
endmodule
endmodule
`timescale 1 ns/1 ns
`timescale 1 ns/1 ns
module vl_gbuf ( i, o);
`define MODULE gbuf
 
module `BASE`MODULE ( i, o);
 
`undef MODULE
input i;
input i;
output o;
output o;
`ifdef SIM_GBUF
`ifdef SIM_GBUF
assign o=i;
assign o=i;
`else
`else
gbuf gbuf_i0 ( .CLK(i), .GL(o));
gbuf gbuf_i0 ( .CLK(i), .GL(o));
`endif
`endif
endmodule
endmodule
 
`endif
 
 
`else
`else
 
 
`ifdef ALTERA
`ifdef ALTERA
 
`ifdef GBUF
//altera
//altera
module vl_gbuf ( i, o);
`define MODULE gbuf
 
module `BASE`MODULE ( i, o);
 
`undef MODULE
input i;
input i;
output o;
output o;
assign o = i;
assign o = i;
endmodule
endmodule
 
`endif
 
 
`else
`else
 
 
 
`ifdef GBUF
`timescale 1 ns/100 ps
`timescale 1 ns/100 ps
module vl_gbuf ( i, o);
`define MODULE
 
module `BASE`MODULE ( i, o);
 
`undef MODULE
input i;
input i;
output o;
output o;
assign o = i;
assign o = i;
endmodule
endmodule
 
`endif
`endif // ALTERA
`endif // ALTERA
`endif //ACTEL
`endif //ACTEL
 
 
 
`ifdef SYNC_RST
// sync reset
// sync reset
// input active lo async reset, normally from external reset generator and/or switch
// input active lo async reset, normally from external reset generator and/or switch
// output active high global reset sync with two DFFs 
// output active high global reset sync with two DFFs 
`timescale 1 ns/100 ps
`timescale 1 ns/100 ps
module vl_sync_rst ( rst_n_i, rst_o, clk);
`define MODULE sync_rst
 
module `BASE`MODULE ( rst_n_i, rst_o, clk);
 
`undef MODULE
input rst_n_i, clk;
input rst_n_i, clk;
output rst_o;
output rst_o;
reg [1:0] tmp;
reg [1:0] tmp;
always @ (posedge clk or negedge rst_n_i)
always @ (posedge clk or negedge rst_n_i)
if (!rst_n_i)
if (!rst_n_i)
        tmp <= 2'b11;
        tmp <= 2'b11;
else
else
        tmp <= {1'b0,tmp[1]};
        tmp <= {1'b0,tmp[1]};
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
`define MODULE gbuf
 
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
 
`undef MODULE
endmodule
endmodule
 
`endif
 
 
 
`ifdef PLL
// vl_pll
// vl_pll
`ifdef ACTEL
`ifdef ACTEL
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
`timescale 1 ps/1 ps
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
`define MODULE pll
 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
 
`undef MODULE
parameter index = 0;
parameter index = 0;
parameter number_of_clk = 1;
parameter number_of_clk = 1;
parameter period_time_0 = 20000;
parameter period_time_0 = 20000;
parameter period_time_1 = 20000;
parameter period_time_1 = 20000;
parameter period_time_2 = 20000;
parameter period_time_2 = 20000;
Line 199... Line 430...
end
end
endgenerate // index==0
endgenerate // index==0
 
 
genvar i;
genvar i;
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
`define MODULE sync_rst
 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
 
`undef MODULE
end
end
endgenerate
endgenerate
endmodule
endmodule
`endif
`endif
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
Line 212... Line 445...
 
 
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`ifdef ALTERA
`ifdef ALTERA
 
 
`timescale 1 ps/1 ps
`timescale 1 ps/1 ps
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
`define MODULE pll
 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
 
`undef MODULE
parameter index = 0;
parameter index = 0;
parameter number_of_clk = 1;
parameter number_of_clk = 1;
parameter period_time_0 = 20000;
parameter period_time_0 = 20000;
parameter period_time_1 = 20000;
parameter period_time_1 = 20000;
parameter period_time_2 = 20000;
parameter period_time_2 = 20000;
Line 337... Line 572...
`endif
`endif
`endif
`endif
 
 
genvar i;
genvar i;
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
`define MODULE sync_rst
 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
 
`undef MODULE
end
end
endgenerate
endgenerate
endmodule
endmodule
`endif
`endif
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
 
 
`else
`else
 
 
// generic PLL
// generic PLL
`timescale 1 ps/1 ps
`timescale 1 ps/1 ps
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
`define MODULE pll
 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
 
`undef MODULE
parameter index = 0;
parameter index = 0;
parameter number_of_clk = 1;
parameter number_of_clk = 1;
parameter period_time_0 = 20000;
parameter period_time_0 = 20000;
parameter period_time_1 = 20000;
parameter period_time_1 = 20000;
parameter period_time_2 = 20000;
parameter period_time_2 = 20000;
Line 375... Line 614...
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
endgenerate
endgenerate
 
 
genvar i;
genvar i;
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
`define MODULE sync_rst
 
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
 
`undef MODULE
end
end
endgenerate
endgenerate
 
 
assign #lock_delay lock = rst_n_i;
assign #lock_delay lock = rst_n_i;
 
 
endmodule
endmodule
 
 
`endif //altera
`endif //altera
`endif //actel
`endif //actel
//////////////////////////////////////////////////////////////////////
`undef MODULE
 
`endif//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile library, registers                                ////
////  Versatile library, registers                                ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Different type of registers                                 ////
////  Different type of registers                                 ////
Line 427... Line 669...
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
module vl_dff ( d, q, clk, rst);
`ifdef DFF
 
`define MODULE dff
 
module `BASE`MODULE ( d, q, clk, rst);
 
`undef MODULE
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = 0;
 
 
        input [width-1:0] d;
        input [width-1:0] d;
        input clk, rst;
        input clk, rst;
Line 443... Line 687...
                q <= reset_value;
                q <= reset_value;
        else
        else
                q <= d;
                q <= d;
 
 
endmodule
endmodule
 
`endif
 
 
module vl_dff_array ( d, q, clk, rst);
`ifdef DFF_ARRAY
 
`define MODULE dff_array
 
module `BASE`MODULE ( d, q, clk, rst);
 
`undef MODULE
 
 
        parameter width = 1;
        parameter width = 1;
        parameter depth = 2;
        parameter depth = 2;
        parameter reset_value = 1'b0;
        parameter reset_value = 1'b0;
 
 
Line 468... Line 716...
        end
        end
 
 
    assign q = q_tmp[depth-1];
    assign q = q_tmp[depth-1];
 
 
endmodule
endmodule
 
`endif
 
 
module vl_dff_ce ( d, ce, q, clk, rst);
`ifdef DFF_CE
 
`define MODULE dff_ce
 
module `BASE`MODULE ( d, ce, q, clk, rst);
 
`undef MODULE
 
 
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = 0;
 
 
        input [width-1:0] d;
        input [width-1:0] d;
Line 486... Line 738...
        else
        else
                if (ce)
                if (ce)
                        q <= d;
                        q <= d;
 
 
endmodule
endmodule
 
`endif
 
 
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
`ifdef DFF_CE_CLEAR
 
`define MODULE dff_ce_clear
 
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
 
`undef MODULE
 
 
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = 0;
 
 
        input [width-1:0] d;
        input [width-1:0] d;
Line 507... Line 763...
                    q <= {width{1'b0}};
                    q <= {width{1'b0}};
                else
                else
                    q <= d;
                    q <= d;
 
 
endmodule
endmodule
 
`endif
 
 
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
`ifdef DF_CE_SET
 
`define MODULE dff_ce_set
 
module `BASE`MODULE ( d, ce, set, q, clk, rst);
 
`undef MODULE
 
 
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = 0;
 
 
        input [width-1:0] d;
        input [width-1:0] d;
Line 528... Line 788...
                    q <= {width{1'b1}};
                    q <= {width{1'b1}};
                else
                else
                    q <= d;
                    q <= d;
 
 
endmodule
endmodule
 
`endif
 
 
module vl_spr ( sp, r, q, clk, rst);
`ifdef SPR
 
`define MODULE spr
 
module `BASE`MODULE ( sp, r, q, clk, rst);
 
`undef MODULE
 
 
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = 0;
 
 
        input sp, r;
        input sp, r;
Line 548... Line 812...
                q <= 1'b1;
                q <= 1'b1;
            else if (r)
            else if (r)
                q <= 1'b0;
                q <= 1'b0;
 
 
endmodule
endmodule
 
`endif
 
 
module vl_srp ( s, rp, q, clk, rst);
`ifdef SRP
 
`define MODULE srp
 
module `BASE`MODULE ( s, rp, q, clk, rst);
 
`undef MODULE
 
 
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = 0;
 
 
        input s, rp;
        input s, rp;
Line 568... Line 836...
                q <= 1'b0;
                q <= 1'b0;
            else if (s)
            else if (s)
                q <= 1'b1;
                q <= 1'b1;
 
 
endmodule
endmodule
 
`endif
 
 
`ifdef ALTERA
`ifdef ALTERA
 
 
 
`ifdef DFF_SR
// megafunction wizard: %LPM_FF%
// megafunction wizard: %LPM_FF%
// GENERATION: STANDARD
// GENERATION: STANDARD
// VERSION: WM1.0
// VERSION: WM1.0
// MODULE: lpm_ff 
// MODULE: lpm_ff 
 
 
Line 609... Line 879...
 
 
 
 
// synopsys translate_off
// synopsys translate_off
`timescale 1 ps / 1 ps
`timescale 1 ps / 1 ps
// synopsys translate_on
// synopsys translate_on
module vl_dff_sr (
`define MODULE dff_sr
 
module `BASE`MODULE (
 
`undef MODULE
 
 
        aclr,
        aclr,
        aset,
        aset,
        clock,
        clock,
        data,
        data,
        q);
        q);
Line 689... Line 962...
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
// Retrieval info: LIB_FILE: lpm
 
`endif
 
 
`else
`else
 
 
 
`ifdef DFF_SR
module vl_dff_sr ( aclr, aset, clock, data, q);
`define MODULE dff_sr
 
module `BASE`MODULE ( aclr, aset, clock, data, q);
 
`undef MODULE
 
 
    input         aclr;
    input         aclr;
    input         aset;
    input         aset;
    input         clock;
    input         clock;
    input         data;
    input         data;
Line 711... Line 986...
       q <= 1'b1;
       q <= 1'b1;
     else
     else
       q <= data;
       q <= data;
 
 
endmodule
endmodule
 
`endif
 
 
`endif
`endif
 
 
// LATCH
// LATCH
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
`ifdef ALTERA
`ifdef ALTERA
module vl_latch ( d, le, q, clk);
 
 
`ifdef LATCH
 
`define MODULE latch
 
module `BASE`MODULE ( d, le, q, clk);
 
`undef MODULE
input d, le;
input d, le;
output q;
output q;
input clk;
input clk;
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
endmodule
endmodule
 
`endif
 
 
`else
`else
module latch ( d, le, q, clk);
 
 
`ifdef LATCH
 
`define MODULE latch
 
module `BASE`MODULE ( d, le, q, clk);
 
`undef MODULE
input d, le;
input d, le;
output q;
output q;
input clk;/*
input clk;/*
   always @ (posedge direction_set or posedge direction_clr)
   always @ (posedge direction_set or posedge direction_clr)
     if (direction_clr)
     if (direction_clr)
Line 736... Line 1022...
     else
     else
       direction <= going_full;*/
       direction <= going_full;*/
endmodule
endmodule
`endif
`endif
 
 
module vl_shreg ( d, q, clk, rst);
`endif
 
 
 
`ifdef SHREG
 
`define MODULE shreg
 
module `BASE`MODULE ( d, q, clk, rst);
 
`undef MODULE
 
 
parameter depth = 10;
parameter depth = 10;
input d;
input d;
output q;
output q;
input clk, rst;
input clk, rst;
 
 
Line 751... Line 1043...
    dffs <= {depth{1'b0}};
    dffs <= {depth{1'b0}};
else
else
    dffs <= {d,dffs[1:depth-1]};
    dffs <= {d,dffs[1:depth-1]};
assign q = dffs[depth];
assign q = dffs[depth];
endmodule
endmodule
 
`endif
 
 
module vl_shreg_ce ( d, ce, q, clk, rst);
`ifdef SHREG_CE
 
`define MODULE shreg_ce
 
module `BASE`MODULE ( d, ce, q, clk, rst);
 
`undef MODULE
parameter depth = 10;
parameter depth = 10;
input d, ce;
input d, ce;
output q;
output q;
input clk, rst;
input clk, rst;
 
 
Line 768... Line 1064...
else
else
    if (ce)
    if (ce)
        dffs <= {d,dffs[1:depth-1]};
        dffs <= {d,dffs[1:depth-1]};
assign q = dffs[depth];
assign q = dffs[depth];
endmodule
endmodule
 
`endif
 
 
module vl_delay ( d, q, clk, rst);
`ifdef DELAY
 
`define MODULE delay
 
module `BASE`MODULE ( d, q, clk, rst);
 
`undef MODULE
parameter depth = 10;
parameter depth = 10;
input d;
input d;
output q;
output q;
input clk, rst;
input clk, rst;
 
 
Line 784... Line 1084...
    dffs <= {depth{1'b0}};
    dffs <= {depth{1'b0}};
else
else
    dffs <= {d,dffs[1:depth-1]};
    dffs <= {d,dffs[1:depth-1]};
assign q = dffs[depth];
assign q = dffs[depth];
endmodule
endmodule
 
`endif
 
 
 
`ifdef DELAY_EMPTYFLAG
 
`define MODULE delay_emptyflag
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
 
`undef MODULE
parameter depth = 10;
parameter depth = 10;
input d;
input d;
output q, emptyflag;
output q, emptyflag;
input clk, rst;
input clk, rst;
 
 
Line 801... Line 1105...
else
else
    dffs <= {d,dffs[1:depth-1]};
    dffs <= {d,dffs[1:depth-1]};
assign q = dffs[depth];
assign q = dffs[depth];
assign emptyflag = !(|dffs);
assign emptyflag = !(|dffs);
endmodule
endmodule
 
`endif
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Logic functions                                             ////
////  Logic functions                                             ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
Line 842... Line 1147...
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
module vl_mux_andor ( a, sel, dout);
`ifdef MUX_ANDOR
 
`define MODULE mux_andor
 
module `BASE`MODULE ( a, sel, dout);
 
`undef MODULE
 
 
parameter width = 32;
parameter width = 32;
parameter nr_of_ports = 4;
parameter nr_of_ports = 4;
 
 
input [nr_of_ports*width-1:0] a;
input [nr_of_ports*width-1:0] a;
Line 862... Line 1170...
        for (j=0;j<32;j=j+1)
        for (j=0;j<32;j=j+1)
            dout[j] = (a[(i-1)*width + j] & sel[i]) | dout[j];
            dout[j] = (a[(i-1)*width + j] & sel[i]) | dout[j];
end
end
 
 
endmodule
endmodule
 
`endif
 
 
module vl_mux2_andor ( a1, a0, sel, dout);
`ifdef MUX2_ANDOR
 
`define MODULE mux2_andor
 
module `BASE`MODULE ( a1, a0, sel, dout);
 
`undef MODULE
 
 
parameter width = 32;
parameter width = 32;
localparam nr_of_ports = 2;
localparam nr_of_ports = 2;
input [width-1:0] a1, a0;
input [width-1:0] a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
output [width-1:0] dout;
 
 
vl_mux_andor
`define MODULE mux_andor
 
`BASE`MODULE
    # ( .width(width), .nr_of_ports(nr_of_ports))
    # ( .width(width), .nr_of_ports(nr_of_ports))
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
 
`undef MODULE
 
 
endmodule
endmodule
 
`endif
 
 
module vl_mux3_andor ( a2, a1, a0, sel, dout);
`ifdef MUX3_ANDOR
 
`define MODULE mux3_andor
 
module `BASE`MODULE ( a2, a1, a0, sel, dout);
 
`undef MODULE
 
 
parameter width = 32;
parameter width = 32;
localparam nr_of_ports = 3;
localparam nr_of_ports = 3;
input [width-1:0] a2, a1, a0;
input [width-1:0] a2, a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
output [width-1:0] dout;
 
 
vl_mux_andor
`define MODULE mux_andor
 
`BASE`MODULE
    # ( .width(width), .nr_of_ports(nr_of_ports))
    # ( .width(width), .nr_of_ports(nr_of_ports))
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
 
`undef MODULE
endmodule
endmodule
 
`endif
 
 
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
`ifdef MUX4_ANDOR
 
`define MODULE mux4_andor
 
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
 
`undef MODULE
 
 
parameter width = 32;
parameter width = 32;
localparam nr_of_ports = 4;
localparam nr_of_ports = 4;
input [width-1:0] a3, a2, a1, a0;
input [width-1:0] a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
output [width-1:0] dout;
 
 
vl_mux_andor
`define MODULE mux_andor
 
`BASE`MODULE
    # ( .width(width), .nr_of_ports(nr_of_ports))
    # ( .width(width), .nr_of_ports(nr_of_ports))
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
 
`undef MODULE
 
 
endmodule
endmodule
 
`endif
 
 
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
`ifdef MUX5_ANDOR
 
`define MODULE mux5_andor
 
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
 
`undef MODULE
 
 
parameter width = 32;
parameter width = 32;
localparam nr_of_ports = 5;
localparam nr_of_ports = 5;
input [width-1:0] a4, a3, a2, a1, a0;
input [width-1:0] a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
output [width-1:0] dout;
 
 
vl_mux_andor
`define MODULE mux_andor
 
`BASE`MODULE
    # ( .width(width), .nr_of_ports(nr_of_ports))
    # ( .width(width), .nr_of_ports(nr_of_ports))
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
 
`undef MODULE
 
 
endmodule
endmodule
 
`endif
 
 
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
`ifdef MUX6_ANDOR
 
`define MODULE mux6_andor
 
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
 
`undef MODULE
 
 
parameter width = 32;
parameter width = 32;
localparam nr_of_ports = 6;
localparam nr_of_ports = 6;
input [width-1:0] a5, a4, a3, a2, a1, a0;
input [width-1:0] a5, a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
output [width-1:0] dout;
 
 
vl_mux_andor
`define MODULE mux_andor
 
`BASE`MODULE
    # ( .width(width), .nr_of_ports(nr_of_ports))
    # ( .width(width), .nr_of_ports(nr_of_ports))
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
 
`undef MODULE
 
 
endmodule
endmodule
 
`endif
 
`ifdef CNT_BIN
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
Line 975... Line 1314...
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// binary counter
// binary counter
module vl_cnt_bin ( q, rst, clk);
 
 
`define MODULE cnt_bin
 
module `BASE`MODULE (
 
`undef MODULE
 
 q, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   output [length:1] q;
   output [length:1] q;
   input rst;
   input rst;
   input clk;
   input clk;
Line 1000... Line 1343...
       qi <= q_next;
       qi <= q_next;
 
 
   assign q = qi;
   assign q = qi;
 
 
endmodule
endmodule
 
`endif
 
`ifdef CNT_BIN_CLEAR
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
Line 1043... Line 1388...
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// binary counter
// binary counter
module vl_cnt_bin_clear ( clear, q, rst, clk);
 
 
`define MODULE cnt_bin_clear
 
module `BASE`MODULE (
 
`undef MODULE
 
 clear, q, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   input clear;
   input clear;
   output [length:1] q;
   output [length:1] q;
   input rst;
   input rst;
Line 1069... Line 1418...
       qi <= q_next;
       qi <= q_next;
 
 
   assign q = qi;
   assign q = qi;
 
 
endmodule
endmodule
 
`endif
 
`ifdef CNT_BIN_CE
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
Line 1112... Line 1463...
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// binary counter
// binary counter
module vl_cnt_bin_ce ( cke, q, rst, clk);
 
 
`define MODULE cnt_bin_ce
 
module `BASE`MODULE (
 
`undef MODULE
 
 cke, q, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   output [length:1] q;
   output [length:1] q;
   input rst;
   input rst;
Line 1139... Line 1494...
       qi <= q_next;
       qi <= q_next;
 
 
   assign q = qi;
   assign q = qi;
 
 
endmodule
endmodule
 
`endif
 
`ifdef CNT_BIN_CE_CLEAR
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
Line 1182... Line 1539...
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// binary counter
// binary counter
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
 
 
`define MODULE cnt_bin_ce_clear
 
module `BASE`MODULE (
 
`undef MODULE
 
 clear, cke, q, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   input clear;
   input clear;
   input cke;
   input cke;
   output [length:1] q;
   output [length:1] q;
Line 1210... Line 1571...
       qi <= q_next;
       qi <= q_next;
 
 
   assign q = qi;
   assign q = qi;
 
 
endmodule
endmodule
 
`endif
 
`ifdef CNT_BIN_CE_CLEAR_L1_L2
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
Line 1253... Line 1616...
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// binary counter
// binary counter
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk);
 
 
`define MODULE cnt_bin_ce_clear_l1_l2
 
module `BASE`MODULE (
 
`undef MODULE
 
 clear, cke, q, level1, level2, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   input clear;
   input clear;
   input cke;
   input cke;
   output [length:1] q;
   output [length:1] q;
Line 1310... Line 1677...
    else if (q_next == level2_value)
    else if (q_next == level2_value)
        level2 <= 1'b1;
        level2 <= 1'b1;
    else if (qi == level2_value & rew)
    else if (qi == level2_value & rew)
        level2 <= 1'b0;
        level2 <= 1'b0;
endmodule
endmodule
 
`endif
 
`ifdef CNT_BIN_CE_CLEAR_SET_REW
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
Line 1353... Line 1722...
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// binary counter
// binary counter
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
 
 
`define MODULE cnt_bin_ce_clear_set_rew
 
module `BASE`MODULE (
 
`undef MODULE
 
 clear, set, cke, rew, q, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   input clear;
   input clear;
   input set;
   input set;
   input cke;
   input cke;
Line 1385... Line 1758...
       qi <= q_next;
       qi <= q_next;
 
 
   assign q = qi;
   assign q = qi;
 
 
endmodule
endmodule
 
`endif
 
`ifdef CNT_BIN_CE_REW_L1
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
Line 1428... Line 1803...
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// binary counter
// binary counter
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
 
 
`define MODULE cnt_bin_ce_rew_l1
 
module `BASE`MODULE (
 
`undef MODULE
 
 cke, rew, level1, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   input rew;
   input rew;
   output reg level1;
   output reg level1;
Line 1471... Line 1850...
    else if (q_next == level1_value)
    else if (q_next == level1_value)
        level1 <= 1'b1;
        level1 <= 1'b1;
    else if (qi == level1_value & rew)
    else if (qi == level1_value & rew)
        level1 <= 1'b0;
        level1 <= 1'b0;
endmodule
endmodule
 
`endif
 
`ifdef CNT_BIN_CE_REW_ZQ_L1
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
Line 1514... Line 1895...
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// binary counter
// binary counter
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk);
 
 
`define MODULE cnt_bin_ce_rew_zq_l1
 
module `BASE`MODULE (
 
`undef MODULE
 
 cke, rew, zq, level1, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   input rew;
   input rew;
   output reg zq;
   output reg zq;
Line 1565... Line 1950...
    else if (q_next == level1_value)
    else if (q_next == level1_value)
        level1 <= 1'b1;
        level1 <= 1'b1;
    else if (qi == level1_value & rew)
    else if (qi == level1_value & rew)
        level1 <= 1'b0;
        level1 <= 1'b0;
endmodule
endmodule
 
`endif
 
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
Line 1608... Line 1995...
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// binary counter
// binary counter
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk);
 
 
`define MODULE cnt_bin_ce_rew_q_zq_l1
 
module `BASE`MODULE (
 
`undef MODULE
 
 cke, rew, q, zq, level1, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   input rew;
   input rew;
   output [length:1] q;
   output [length:1] q;
Line 1661... Line 2052...
    else if (q_next == level1_value)
    else if (q_next == level1_value)
        level1 <= 1'b1;
        level1 <= 1'b1;
    else if (qi == level1_value & rew)
    else if (qi == level1_value & rew)
        level1 <= 1'b0;
        level1 <= 1'b0;
endmodule
endmodule
 
`endif
 
`ifdef CNT_LFSR_ZQ
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
Line 1704... Line 2097...
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// LFSR counter
// LFSR counter
module vl_cnt_lfsr_zq ( zq, rst, clk);
 
 
`define MODULE cnt_lfsr_zq
 
module `BASE`MODULE (
 
`undef MODULE
 
 zq, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   output reg zq;
   output reg zq;
   input rst;
   input rst;
   input clk;
   input clk;
Line 1780... Line 2177...
     if (rst)
     if (rst)
       zq <= 1'b1;
       zq <= 1'b1;
     else
     else
       zq <= q_next == {length{1'b0}};
       zq <= q_next == {length{1'b0}};
endmodule
endmodule
 
`endif
 
`ifdef CNT_LFSR_CE_ZQ
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
Line 1823... Line 2222...
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// LFSR counter
// LFSR counter
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
 
 
`define MODULE cnt_lfsr_ce_zq
 
module `BASE`MODULE (
 
`undef MODULE
 
 cke, zq, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   output reg zq;
   output reg zq;
   input rst;
   input rst;
Line 1902... Line 2305...
       zq <= 1'b1;
       zq <= 1'b1;
     else
     else
     if (cke)
     if (cke)
       zq <= q_next == {length{1'b0}};
       zq <= q_next == {length{1'b0}};
endmodule
endmodule
 
`endif
 
`ifdef CNT_LFSR_CE_Q
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
Line 1945... Line 2350...
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// LFSR counter
// LFSR counter
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk);
 
 
`define MODULE cnt_lfsr_ce_q
 
module `BASE`MODULE (
 
`undef MODULE
 
 cke, q, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   output [length:1] q;
   output [length:1] q;
   input rst;
   input rst;
Line 2018... Line 2427...
       qi <= q_next;
       qi <= q_next;
 
 
   assign q = qi;
   assign q = qi;
 
 
endmodule
endmodule
 
`endif
 
`ifdef CNT_LFSR_CE_CLEAR_Q
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
Line 2061... Line 2472...
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// LFSR counter
// LFSR counter
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk);
 
 
`define MODULE cnt_lfsr_ce_clear_q
 
module `BASE`MODULE (
 
`undef MODULE
 
 clear, cke, q, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   input clear;
   input clear;
   input cke;
   input cke;
   output [length:1] q;
   output [length:1] q;
Line 2135... Line 2550...
       qi <= q_next;
       qi <= q_next;
 
 
   assign q = qi;
   assign q = qi;
 
 
endmodule
endmodule
 
`endif
 
`ifdef CNT_LFSR_CE_Q_ZQ
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
Line 2178... Line 2595...
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// LFSR counter
// LFSR counter
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
 
 
`define MODULE cnt_lfsr_ce_q_zq
 
module `BASE`MODULE (
 
`undef MODULE
 
 cke, q, zq, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   output [length:1] q;
   output [length:1] q;
   output reg zq;
   output reg zq;
Line 2259... Line 2680...
       zq <= 1'b1;
       zq <= 1'b1;
     else
     else
     if (cke)
     if (cke)
       zq <= q_next == {length{1'b0}};
       zq <= q_next == {length{1'b0}};
endmodule
endmodule
 
`endif
 
`ifdef CNT_LFSR_CE_REW_L1
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
Line 2302... Line 2725...
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// LFSR counter
// LFSR counter
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
 
 
`define MODULE cnt_lfsr_ce_rew_l1
 
module `BASE`MODULE (
 
`undef MODULE
 
 cke, rew, level1, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   input rew;
   input rew;
   output reg level1;
   output reg level1;
Line 2437... Line 2864...
    else if (q_next == level1_value)
    else if (q_next == level1_value)
        level1 <= 1'b1;
        level1 <= 1'b1;
    else if (qi == level1_value & rew)
    else if (qi == level1_value & rew)
        level1 <= 1'b0;
        level1 <= 1'b0;
endmodule
endmodule
 
`endif
 
`ifdef CNT_GRAY
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
Line 2480... Line 2909...
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// GRAY counter
// GRAY counter
module vl_cnt_gray ( q, rst, clk);
 
 
`define MODULE cnt_gray
 
module `BASE`MODULE (
 
`undef MODULE
 
 q, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   output reg [length:1] q;
   output reg [length:1] q;
   input rst;
   input rst;
   input clk;
   input clk;
Line 2509... Line 2942...
       q <= {length{1'b0}};
       q <= {length{1'b0}};
     else
     else
         q <= (q_next>>1) ^ q_next;
         q <= (q_next>>1) ^ q_next;
 
 
endmodule
endmodule
 
`endif
 
`ifdef CNT_GRAY_CE
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
Line 2552... Line 2987...
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// GRAY counter
// GRAY counter
module vl_cnt_gray_ce ( cke, q, rst, clk);
 
 
`define MODULE cnt_gray_ce
 
module `BASE`MODULE (
 
`undef MODULE
 
 cke, q, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   output reg [length:1] q;
   output reg [length:1] q;
   input rst;
   input rst;
Line 2584... Line 3023...
     else
     else
       if (cke)
       if (cke)
         q <= (q_next>>1) ^ q_next;
         q <= (q_next>>1) ^ q_next;
 
 
endmodule
endmodule
 
`endif
 
`ifdef CNT_GRAY_CE_BIN
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
Line 2627... Line 3068...
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
// GRAY counter
// GRAY counter
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
 
 
`define MODULE cnt_gray_ce_bin
 
module `BASE`MODULE (
 
`undef MODULE
 
 cke, q, q_bin, rst, clk);
 
 
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   output reg [length:1] q;
   output reg [length:1] q;
   output [length:1] q_bin;
   output [length:1] q_bin;
Line 2662... Line 3107...
         q <= (q_next>>1) ^ q_next;
         q <= (q_next>>1) ^ q_next;
 
 
   assign q_bin = qi;
   assign q_bin = qi;
 
 
endmodule
endmodule
 
`endif
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile library, counters                                 ////
////  Versatile library, counters                                 ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
Line 2704... Line 3150...
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
module vl_cnt_shreg_wrap ( q, rst, clk);
`ifdef CNT_SHREG_WRAP
 
`define MODULE cnt_shreg_wrap
 
module `BASE`MODULE ( q, rst, clk);
 
`undef MODULE
 
 
   parameter length = 4;
   parameter length = 4;
   output reg [0:length-1] q;
   output reg [0:length-1] q;
   input rst;
   input rst;
   input clk;
   input clk;
Line 2718... Line 3167...
        q <= {1'b1,{length-1{1'b0}}};
        q <= {1'b1,{length-1{1'b0}}};
    else
    else
        q <= {q[length-1],q[0:length-2]};
        q <= {q[length-1],q[0:length-2]};
 
 
endmodule
endmodule
 
`endif
 
 
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
`ifdef CNT_SHREG_CE_WRAP
 
`define MODULE cnt_shreg_ce_wrap
 
module `BASE`MODULE ( cke, q, rst, clk);
 
`undef MODULE
 
 
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   output reg [0:length-1] q;
   output reg [0:length-1] q;
   input rst;
   input rst;
Line 2735... Line 3188...
    else
    else
        if (cke)
        if (cke)
            q <= {q[length-1],q[0:length-2]};
            q <= {q[length-1],q[0:length-2]};
 
 
endmodule
endmodule
 
`endif
 
 
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
`ifdef CNT_SHREG_CE_CLEAR
 
`define MODULE cnt_shreg_ce_clear
 
module `BASE`MODULE ( cke, clear, q, rst, clk);
 
`undef MODULE
 
 
   parameter length = 4;
   parameter length = 4;
   input cke, clear;
   input cke, clear;
   output reg [0:length-1] q;
   output reg [0:length-1] q;
   input rst;
   input rst;
Line 2755... Line 3212...
                q <= {1'b1,{length-1{1'b0}}};
                q <= {1'b1,{length-1{1'b0}}};
            else
            else
                q <= q >> 1;
                q <= q >> 1;
 
 
endmodule
endmodule
 
`endif
 
 
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
`ifdef CNT_SHREG_CE_CLEAR_WRAP
 
`define MODULE cnt_shreg_ce_clear_wrap
 
module `BASE`MODULE ( cke, clear, q, rst, clk);
 
`undef MODULE
 
 
   parameter length = 4;
   parameter length = 4;
   input cke, clear;
   input cke, clear;
   output reg [0:length-1] q;
   output reg [0:length-1] q;
   input rst;
   input rst;
Line 2775... Line 3236...
                q <= {1'b1,{length-1{1'b0}}};
                q <= {1'b1,{length-1{1'b0}}};
            else
            else
            q <= {q[length-1],q[0:length-2]};
            q <= {q[length-1],q[0:length-2]};
 
 
endmodule
endmodule
 
`endif
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile library, memories                                 ////
////  Versatile library, memories                                 ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
Line 2817... Line 3279...
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
 
`ifdef ROM_INIT
/// ROM
/// ROM
 
`define MODULE rom_init
 
module `BASE`MODULE ( adr, q, clk);
 
`undef MODULE
 
 
module vl_rom_init ( adr, q, clk);
 
   parameter data_width = 32;
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter addr_width = 8;
   input [(addr_width-1):0]       adr;
   input [(addr_width-1):0]       adr;
   output reg [(data_width-1):0] q;
   output reg [(data_width-1):0] q;
   input                         clk;
   input                         clk;
Line 2836... Line 3301...
 
 
   always @ (posedge clk)
   always @ (posedge clk)
     q <= rom[adr];
     q <= rom[adr];
 
 
endmodule
endmodule
 
`endif
 
 
/*
/*
module vl_rom ( adr, q, clk);
module vl_rom ( adr, q, clk);
 
 
parameter data_width = 32;
parameter data_width = 32;
Line 2870... Line 3336...
always @ (posedge clk)
always @ (posedge clk)
    q <= data[adr];
    q <= data[adr];
 
 
endmodule
endmodule
*/
*/
 
 
 
`ifdef RAM
 
`define MODULE ram
// Single port RAM
// Single port RAM
 
module `BASE`MODULE ( d, adr, we, q, clk);
 
`undef MODULE
 
 
module vl_ram ( d, adr, we, q, clk);
 
   parameter data_width = 32;
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter addr_width = 8;
   input [(data_width-1):0]      d;
   input [(data_width-1):0]      d;
   input [(addr_width-1):0]       adr;
   input [(addr_width-1):0]       adr;
   input                         we;
   input                         we;
Line 2899... Line 3369...
     ram[adr] <= d;
     ram[adr] <= d;
   q <= ram[adr];
   q <= ram[adr];
   end
   end
 
 
endmodule
endmodule
 
`endif
 
 
 
`ifdef RAM_BE
 
`define MODULE ram_be
 
module `BASE`MODULE ( d, adr, be, we, q, clk);
 
`undef MODULE
 
 
module vl_ram_be ( d, adr, be, we, q, clk);
 
   parameter data_width = 32;
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter addr_width = 8;
   input [(data_width-1):0]      d;
   input [(data_width-1):0]      d;
   input [(addr_width-1):0]       adr;
   input [(addr_width-1):0]       adr;
   input [(addr_width/4)-1:0]    be;
   input [(addr_width/4)-1:0]    be;
Line 2934... Line 3409...
 
 
   always @ (posedge clk)
   always @ (posedge clk)
      q <= ram[adr];
      q <= ram[adr];
 
 
endmodule
endmodule
 
`endif
 
 
// Dual port RAM
// Dual port RAM
 
 
// ACTEL FPGA should not use logic to handle rw collision
// ACTEL FPGA should not use logic to handle rw collision
`ifdef ACTEL
`ifdef ACTEL
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
`else
`else
        `define SYN
        `define SYN
`endif
`endif
 
 
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
`ifdef DPRAM_1R1W
 
`define MODULE dpram_1r1w
 
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
 
`undef MODULE
   parameter data_width = 32;
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter addr_width = 8;
   input [(data_width-1):0]      d_a;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input [(addr_width-1):0]       adr_b;
Line 2973... Line 3451...
   if (we_a)
   if (we_a)
     ram[adr_a] <= d_a;
     ram[adr_a] <= d_a;
   always @ (posedge clk_b)
   always @ (posedge clk_b)
   adr_b_reg <= adr_b;
   adr_b_reg <= adr_b;
   assign q_b = ram[adr_b_reg];
   assign q_b = ram[adr_b_reg];
 
 
endmodule
endmodule
 
`endif
 
 
 
`ifdef DPRAM_2R1W
 
`define MODULE dpram_2r1w
 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
 
`undef MODULE
 
 
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
 
   parameter data_width = 32;
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter addr_width = 8;
   input [(data_width-1):0]      d_a;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input [(addr_width-1):0]       adr_b;
Line 3007... Line 3491...
             ram[adr_a] <= d_a;
             ram[adr_a] <= d_a;
     end
     end
   always @ (posedge clk_b)
   always @ (posedge clk_b)
          q_b <= ram[adr_b];
          q_b <= ram[adr_b];
endmodule
endmodule
 
`endif
 
 
 
`ifdef DPRAM_2R2W
 
`define MODULE dpram_2r2w
 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
 
`undef MODULE
 
 
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
 
   parameter data_width = 32;
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter addr_width = 8;
   input [(data_width-1):0]      d_a;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input [(addr_width-1):0]       adr_b;
Line 3046... Line 3535...
        q_b <= ram[adr_b];
        q_b <= ram[adr_b];
        if (we_b)
        if (we_b)
          ram[adr_b] <= d_b;
          ram[adr_b] <= d_b;
     end
     end
endmodule
endmodule
 
`endif
 
 
// Content addresable memory, CAM
// Content addresable memory, CAM
 
 
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
// FIFO
// FIFO
module vl_fifo_1r1w_fill_level_sync (
`define MODULE fifo_1r1w_fill_level_sync
 
module `BASE`MODULE (
 
`undef MODULE
    d, wr, fifo_full,
    d, wr, fifo_full,
    q, rd, fifo_empty,
    q, rd, fifo_empty,
    fill_level,
    fill_level,
    clk, rst
    clk, rst
    );
    );
Line 3074... Line 3567...
output [addr_width:0]   fill_level;
output [addr_width:0]   fill_level;
input rst, clk;
input rst, clk;
 
 
wire [addr_width:1] wadr, radr;
wire [addr_width:1] wadr, radr;
 
 
vl_cnt_bin_ce
`define MODULE cnt_bin_ce
 
`BASE`MODULE
    # ( .length(addr_width))
    # ( .length(addr_width))
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
 
`BASE`MODULE
vl_cnt_bin_ce
 
    # (.length(addr_width))
    # (.length(addr_width))
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
 
`undef MODULE
 
 
vl_dpram_1r1w
`define MODULE dpram_1r1w
 
`BASE`MODULE
    # (.data_width(data_width), .addr_width(addr_width))
    # (.data_width(data_width), .addr_width(addr_width))
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
 
`undef MODULE
 
 
vl_cnt_bin_ce_rew_q_zq_l1
`define MODULE cnt_bin_ce_rew_q_zq_l1
 
`BASE`MODULE
    # (.length(addr_width+1), .level1_value(1<<addr_width))
    # (.length(addr_width+1), .level1_value(1<<addr_width))
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
 
`undef MODULE
endmodule
endmodule
 
`endif
 
 
 
`ifdef FIFO_2R2W_SYNC_SIMPLEX
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
// RAM is supposed to be larger than the two FIFOs
// RAM is supposed to be larger than the two FIFOs
// LFSR counters used adr pointers
// LFSR counters used adr pointers
module vl_fifo_2r2w_sync_simplex (
`define MODULE fifo_2r2w_sync_simplex
 
module `BASE`MODULE (
 
`undef MODULE
    // a side
    // a side
    a_d, a_wr, a_fifo_full,
    a_d, a_wr, a_fifo_full,
    a_q, a_rd, a_fifo_empty,
    a_q, a_rd, a_fifo_empty,
    a_fill_level,
    a_fill_level,
    // b side
    // b side
Line 3138... Line 3639...
wire [addr_width:1] a_wadr, a_radr;
wire [addr_width:1] a_wadr, a_radr;
wire [addr_width:1] b_wadr, b_radr;
wire [addr_width:1] b_wadr, b_radr;
// dpram
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
 
 
vl_cnt_lfsr_ce
`define MODULE cnt_lfsr_ce
 
`BASE`MODULE
    # ( .length(addr_width))
    # ( .length(addr_width))
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
 
 
vl_cnt_lfsr_ce
`BASE`MODULE
    # (.length(addr_width))
    # (.length(addr_width))
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
 
 
vl_cnt_lfsr_ce
`BASE`MODULE
    # ( .length(addr_width))
    # ( .length(addr_width))
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
 
 
vl_cnt_lfsr_ce
`BASE`MODULE
    # (.length(addr_width))
    # (.length(addr_width))
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
 
`undef MODULE
 
 
// mux read or write adr to DPRAM
// mux read or write adr to DPRAM
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
 
 
vl_dpram_2r2w
`define MODULE dpram_2r2w
 
`BASE`MODULE
    # (.data_width(data_width), .addr_width(addr_width+1))
    # (.data_width(data_width), .addr_width(addr_width+1))
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
 
`undef MODULE
 
 
vl_cnt_bin_ce_rew_zq_l1
`define MODULE cnt_bin_ce_rew_zq_l1
 
`BASE`MODULE
    # (.length(addr_width), .level1_value(fifo_full_level))
    # (.length(addr_width), .level1_value(fifo_full_level))
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
 
 
vl_cnt_bin_ce_rew_zq_l1
`BASE`MODULE
    # (.length(addr_width), .level1_value(fifo_full_level))
    # (.length(addr_width), .level1_value(fifo_full_level))
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
 
`undef MODULE
 
 
endmodule
endmodule
 
`endif
 
 
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
`ifdef FIFO_CMP_ASYNC
 
`define MODULE fifo_cmp_async
 
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
 
`undef MODULE
 
 
   parameter addr_width = 4;
   parameter addr_width = 4;
   parameter N = addr_width-1;
   parameter N = addr_width-1;
 
 
   parameter Q1 = 2'b00;
   parameter Q1 = 2'b00;
Line 3226... Line 3737...
         {Q4,Q3} : direction_clr <= 1'b1;
         {Q4,Q3} : direction_clr <= 1'b1;
         {Q1,Q4} : direction_clr <= 1'b1;
         {Q1,Q4} : direction_clr <= 1'b1;
         default : direction_clr <= 1'b0;
         default : direction_clr <= 1'b0;
       endcase
       endcase
 
 
 
`define MODULE dff_sr
`ifndef GENERATE_DIRECTION_AS_LATCH
`ifndef GENERATE_DIRECTION_AS_LATCH
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
`endif
`endif
 
 
`ifdef GENERATE_DIRECTION_AS_LATCH
`ifdef GENERATE_DIRECTION_AS_LATCH
   always @ (posedge direction_set or posedge direction_clr)
   always @ (posedge direction_set or posedge direction_clr)
     if (direction_clr)
     if (direction_clr)
Line 3241... Line 3753...
`endif
`endif
 
 
   assign async_empty = (wptr == rptr) && (direction==going_empty);
   assign async_empty = (wptr == rptr) && (direction==going_empty);
   assign async_full  = (wptr == rptr) && (direction==going_full);
   assign async_full  = (wptr == rptr) && (direction==going_full);
 
 
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
 
`undef MODULE
 
 
/*
/*
   always @ (posedge wclk or posedge rst or posedge async_full)
   always @ (posedge wclk or posedge rst or posedge async_full)
     if (rst)
     if (rst)
       {fifo_full, fifo_full2} <= 2'b00;
       {fifo_full, fifo_full2} <= 2'b00;
Line 3258... Line 3771...
/*   always @ (posedge rclk or posedge async_empty)
/*   always @ (posedge rclk or posedge async_empty)
     if (async_empty)
     if (async_empty)
       {fifo_empty, fifo_empty2} <= 2'b11;
       {fifo_empty, fifo_empty2} <= 2'b11;
     else
     else
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
`define MODULE dff
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
 
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
 
`undef MODULE
endmodule // async_compb
endmodule // async_compb
 
`endif
 
 
module vl_fifo_1r1w_async (
`ifdef FIFO_1R1W_ASYNC
 
`define MODULE fifo_1r1w_async
 
module `BASE`MODULE (
 
`undef MODULE
    d, wr, fifo_full, wr_clk, wr_rst,
    d, wr, fifo_full, wr_clk, wr_rst,
    q, rd, fifo_empty, rd_clk, rd_rst
    q, rd, fifo_empty, rd_clk, rd_rst
    );
    );
 
 
parameter data_width = 18;
parameter data_width = 18;
Line 3286... Line 3804...
input                   rd_clk;
input                   rd_clk;
input                   rd_rst;
input                   rd_rst;
 
 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
 
 
vl_cnt_gray_ce_bin
`define MODULE cnt_gray_ce_bin
 
`BASE`MODULE
    # ( .length(addr_width))
    # ( .length(addr_width))
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
 
 
vl_cnt_gray_ce_bin
`BASE`MODULE
    # (.length(addr_width))
    # (.length(addr_width))
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
 
`undef MODULE
 
 
vl_dpram_1r1w
`define MODULE dpram_1r1w
 
`BASE`MODULE
    # (.data_width(data_width), .addr_width(addr_width))
    # (.data_width(data_width), .addr_width(addr_width))
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
 
`undef MODULE
 
 
vl_fifo_cmp_async
`define MODULE fifo_cmp_async
 
`BASE`MODULE
    # (.addr_width(addr_width))
    # (.addr_width(addr_width))
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
 
`undef MODULE
 
 
endmodule
endmodule
 
`endif
 
 
module vl_fifo_2r2w_async (
`ifdef FIFO_2R2W_ASYNC
 
`define MODULE fifo_2r2w_async
 
module `BASE`MODULE (
 
`undef MODULE
    // a side
    // a side
    a_d, a_wr, a_fifo_full,
    a_d, a_wr, a_fifo_full,
    a_q, a_rd, a_fifo_empty,
    a_q, a_rd, a_fifo_empty,
    a_clk, a_rst,
    a_clk, a_rst,
    // b side
    // b side
Line 3338... Line 3866...
input                   b_rd;
input                   b_rd;
output                  b_fifo_empty;
output                  b_fifo_empty;
input                   b_clk;
input                   b_clk;
input                   b_rst;
input                   b_rst;
 
 
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
`define MODULE fifo_1r1w_async
 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
vl_fifo_1r1w_async_a (
vl_fifo_1r1w_async_a (
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
    );
    );
 
 
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
vl_fifo_1r1w_async_b (
vl_fifo_1r1w_async_b (
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
    );
    );
 
`undef MODULE
 
 
endmodule
endmodule
 
`endif
 
 
module vl_fifo_2r2w_async_simplex (
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
 
`define MODULE fifo_2r2w_async_simplex
 
module `BASE`MODULE (
 
`undef MODULE
    // a side
    // a side
    a_d, a_wr, a_fifo_full,
    a_d, a_wr, a_fifo_full,
    a_q, a_rd, a_fifo_empty,
    a_q, a_rd, a_fifo_empty,
    a_clk, a_rst,
    a_clk, a_rst,
    // b side
    // b side
Line 3392... Line 3926...
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
// dpram
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
 
 
vl_cnt_gray_ce_bin
`define MODULE cnt_gray_ce_bin
 
`BASE`MODULE
    # ( .length(addr_width))
    # ( .length(addr_width))
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
 
 
vl_cnt_gray_ce_bin
`BASE`MODULE
    # (.length(addr_width))
    # (.length(addr_width))
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
 
 
vl_cnt_gray_ce_bin
`BASE`MODULE
    # ( .length(addr_width))
    # ( .length(addr_width))
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
 
 
vl_cnt_gray_ce_bin
`BASE`MODULE
    # (.length(addr_width))
    # (.length(addr_width))
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
 
`undef MODULE
 
 
// mux read or write adr to DPRAM
// mux read or write adr to DPRAM
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
 
 
vl_dpram_2r2w
`define MODULE dpram_2r2w
 
`BASE`MODULE
    # (.data_width(data_width), .addr_width(addr_width+1))
    # (.data_width(data_width), .addr_width(addr_width+1))
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
 
`undef MODULE
 
 
vl_fifo_cmp_async
`define MODULE fifo_cmp_async
 
`BASE`MODULE
    # (.addr_width(addr_width))
    # (.addr_width(addr_width))
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
 
 
vl_fifo_cmp_async
`BASE`MODULE
    # (.addr_width(addr_width))
    # (.addr_width(addr_width))
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
 
`undef MODULE
 
 
endmodule
endmodule
 
`endif
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile library, wishbone stuff                           ////
////  Versatile library, wishbone stuff                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
Line 3468... Line 4009...
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
 
`ifdef WB3WB3_BRIDGE
// async wb3 - wb3 bridge
// async wb3 - wb3 bridge
`timescale 1ns/1ns
`timescale 1ns/1ns
module vl_wb3wb3_bridge (
`define MODULE wb3wb3_bridge
 
module `BASE`MODULE (
 
`undef MODULE
        // wishbone slave side
        // wishbone slave side
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
        // wishbone master side
        // wishbone master side
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
 
 
Line 3547... Line 4091...
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
                wbs_eoc <= wbs_bte_i==linear;
                wbs_eoc <= wbs_bte_i==linear;
        else if (wbs_eoc_alert & (a_rd | a_wr))
        else if (wbs_eoc_alert & (a_rd | a_wr))
                wbs_eoc <= 1'b1;
                wbs_eoc <= 1'b1;
 
 
vl_cnt_shreg_ce_clear # ( .length(16))
`define MODULE cnt_shreg_ce_clear
 
`BASE`MODULE # ( .length(16))
 
`undef MODULE
    cnt0 (
    cnt0 (
        .cke(wbs_ack_o),
        .cke(wbs_ack_o),
        .clear(wbs_eoc),
        .clear(wbs_eoc),
        .q(wbs_count),
        .q(wbs_count),
        .rst(wbs_rst),
        .rst(wbs_rst),
Line 3633... Line 4179...
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
                   1'b0;
                   1'b0;
assign b_rd = b_rd_adr | b_rd_data;
assign b_rd = b_rd_adr | b_rd_data;
 
 
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
`define MODULE dff
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
 
`undef MODULE
 
`define MODULE dff_ce
 
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
 
`undef MODULE
 
 
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
 
 
 
`define MODULE cnt_shreg_ce_clear
vl_cnt_shreg_ce_clear # ( .length(16))
vl_cnt_shreg_ce_clear # ( .length(16))
 
`undef MODULE
    cnt1 (
    cnt1 (
        .cke(wbm_ack_i),
        .cke(wbm_ack_i),
        .clear(wbm_eoc),
        .clear(wbm_eoc),
        .q(wbm_count),
        .q(wbm_count),
        .rst(wbm_rst),
        .rst(wbm_rst),
Line 3660... Line 4212...
        else if (wbm_eoc_alert & wbm_ack_i)
        else if (wbm_eoc_alert & wbm_ack_i)
                wbm_cti_o <= endofburst;
                wbm_cti_o <= endofburst;
end
end
 
 
//async_fifo_dw_simplex_top
//async_fifo_dw_simplex_top
vl_fifo_2r2w_async_simplex
`define MODULE fifo_2r2w_async_simplex
 
`BASE`MODULE
 
`undef MODULE
# ( .data_width(36), .addr_width(addr_width))
# ( .data_width(36), .addr_width(addr_width))
fifo (
fifo (
    // a side
    // a side
    .a_d(a_d),
    .a_d(a_d),
    .a_wr(a_wr),
    .a_wr(a_wr),
Line 3684... Line 4238...
    .b_clk(wbm_clk),
    .b_clk(wbm_clk),
    .b_rst(wbm_rst)
    .b_rst(wbm_rst)
    );
    );
 
 
endmodule
endmodule
 
`undef WE
 
`undef BTE
 
`undef CTI
 
`endif
 
 
 
`ifdef WB3_ARBITER_TYPE1
 
`define MODULE wb3_arbiter_type1
module vl_wb3_arbiter_type1 (
module vl_wb3_arbiter_type1 (
 
`undef MODULE
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
    wb_clk, wb_rst
    wb_clk, wb_rst
Line 3772... Line 4333...
end
end
endgenerate
endgenerate
 
 
    assign sel = select | state;
    assign sel = select | state;
 
 
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
`define MODULE mux_andor
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
 
`undef MODULE
    assign wbs_cyc_i = |sel;
    assign wbs_cyc_i = |sel;
 
 
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
 
 
endmodule
endmodule
 
`endif
 
 
 
`ifdef WB_BOOT_ROM
// WB ROM
// WB ROM
module vl_wb_boot_rom (
`define MODULE wb_boot_rom
 
module `BASE`MODULE (
 
`undef MODULE
    wb_adr_i, wb_stb_i, wb_cyc_i,
    wb_adr_i, wb_stb_i, wb_cyc_i,
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
 
 
    parameter adr_hi = 31;
    parameter adr_hi = 31;
    parameter adr_lo = 28;
    parameter adr_lo = 28;
Line 3850... Line 4417...
assign hit_o = hit;
assign hit_o = hit;
assign wb_dat_o = wb_dat & {32{wb_ack}};
assign wb_dat_o = wb_dat & {32{wb_ack}};
assign wb_ack_o = wb_ack;
assign wb_ack_o = wb_ack;
 
 
endmodule
endmodule
 
`endif
 
 
module vl_wb_dpram (
`ifdef WB_DPRAM
 
`define MODULE wb_dpram
 
module `BASE`MODULE (
 
`undef MODULE
        // wishbone slave side a
        // wishbone slave side a
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
        wbsa_clk, wbsa_rst,
        wbsa_clk, wbsa_rst,
        // wishbone slave side a
        // wishbone slave side a
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
Line 3881... Line 4452...
output wbsb_ack_o;
output wbsb_ack_o;
input wbsb_clk, wbsb_rst;
input wbsb_clk, wbsb_rst;
 
 
wire wbsa_dat_tmp, wbsb_dat_tmp;
wire wbsa_dat_tmp, wbsb_dat_tmp;
 
 
vl_dpram_2r2w # (
`define MODULE dpram_2r2w
 
`BASE`MODULE # (
 
`undef MODULE
    .data_width(data_width), .addr_width(addr_width) )
    .data_width(data_width), .addr_width(addr_width) )
dpram0(
dpram0(
    .d_a(wbsa_dat_i),
    .d_a(wbsa_dat_i),
    .q_a(wbsa_dat_tmp),
    .q_a(wbsa_dat_tmp),
    .adr_a(wbsa_adr_i),
    .adr_a(wbsa_adr_i),
Line 3909... Line 4482...
endgenerate
endgenerate
generate if (dat_o_mask_b==0)
generate if (dat_o_mask_b==0)
    assign wbsb_dat_o = wbsb_dat_tmp;
    assign wbsb_dat_o = wbsb_dat_tmp;
endgenerate
endgenerate
 
 
vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
`define MODULE spr
vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
 
`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
 
`undef MODULE
 
 
endmodule
endmodule
 
`endif
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Arithmetic functions                                        ////
////  Arithmetic functions                                        ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
Line 3955... Line 4531...
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
 
`ifdef MULTS
// signed multiplication
// signed multiplication
module vl_mults (a,b,p);
`define MODULE mults
 
module `BASE`MODULE (a,b,p);
 
`undef MODULE
parameter operand_a_width = 18;
parameter operand_a_width = 18;
parameter operand_b_width = 18;
parameter operand_b_width = 18;
parameter result_hi = 35;
parameter result_hi = 35;
parameter result_lo = 0;
parameter result_lo = 0;
input [operand_a_width-1:0] a;
input [operand_a_width-1:0] a;
Line 3974... Line 4553...
    assign bi = b;
    assign bi = b;
    assign result = ai * bi;
    assign result = ai * bi;
    assign p = result[result_hi:result_lo];
    assign p = result[result_hi:result_lo];
 
 
endmodule
endmodule
 
`endif
module vl_mults18x18 (a,b,p);
`ifdef MULTS18X18
 
`define MODULE mults18x18
 
module `BASE`MODULE (a,b,p);
 
`undef MODULE
input [17:0] a,b;
input [17:0] a,b;
output [35:0] p;
output [35:0] p;
vl_mult
vl_mult
    # (.operand_a_width(18), .operand_b_width(18))
    # (.operand_a_width(18), .operand_b_width(18))
    mult0 (.a(a), .b(b), .p(p));
    mult0 (.a(a), .b(b), .p(p));
endmodule
endmodule
 
`endif
 
 
 
`ifdef MULT
 
`define MODULE mult
// unsigned multiplication
// unsigned multiplication
module vl_mult (a,b,p);
module `BASE`MODULE (a,b,p);
 
`undef MODULE
parameter operand_a_width = 18;
parameter operand_a_width = 18;
parameter operand_b_width = 18;
parameter operand_b_width = 18;
parameter result_hi = 35;
parameter result_hi = 35;
parameter result_lo = 0;
parameter result_lo = 0;
input [operand_a_width-1:0] a;
input [operand_a_width-1:0] a;
Line 3999... Line 4585...
 
 
    assign result = a * b;
    assign result = a * b;
    assign p = result[result_hi:result_lo];
    assign p = result[result_hi:result_lo];
 
 
endmodule
endmodule
 
`endif
 
 
 
`ifdef SHIFT_UNIT_32
 
`define MODULE shift_unit_32
// shift unit
// shift unit
// supporting the following shift functions
// supporting the following shift functions
//   SLL
//   SLL
//   SRL
//   SRL
//   SRA
//   SRA
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
module vl_shift_unit_32( din, s, dout, opcode);
module `BASE`MODULE( din, s, dout, opcode);
 
`undef MODULE
input [31:0] din; // data in operand
input [31:0] din; // data in operand
input [4:0] s; // shift operand
input [4:0] s; // shift operand
input [1:0] opcode;
input [1:0] opcode;
output [31:0] dout;
output [31:0] dout;
 
 
Line 4047... Line 4637...
 
 
assign sign[3] = din[31] & sra;
assign sign[3] = din[31] & sra;
assign sign[2] = sign[3] & (&din[31:24]);
assign sign[2] = sign[3] & (&din[31:24]);
assign sign[1] = sign[2] & (&din[23:16]);
assign sign[1] = sign[2] & (&din[23:16]);
assign sign[0] = sign[1] & (&din[15:8]);
assign sign[0] = sign[1] & (&din[15:8]);
vl_mults `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
`define MODULE mults
vl_mults `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
vl_mults `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
vl_mults `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
 
`undef MODULE
// second stage is multiplexer based
// second stage is multiplexer based
// shift on byte level
// shift on byte level
 
 
// mux byte 3
// mux byte 3
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
Line 4087... Line 4678...
                     (s[4:3]==2'b01) ? tmp[1] :
                     (s[4:3]==2'b01) ? tmp[1] :
                     (s[4:3]==2'b10) ? tmp[2] :
                     (s[4:3]==2'b10) ? tmp[2] :
                     tmp[3];
                     tmp[3];
 
 
endmodule
endmodule
 
`endif
 
 
 
`ifdef LOGIC_UNIT
// logic unit
// logic unit
// supporting the following logic functions
// supporting the following logic functions
//    a and b
//    a and b
//    a or  b
//    a or  b
//    a xor b
//    a xor b
//    not b
//    not b
module vl_logic_unit( a, b, result, opcode);
`define MODULE logic_unit
 
module `BASE`MODULE( a, b, result, opcode);
 
`undef MODULE
parameter width = 32;
parameter width = 32;
parameter opcode_and = 2'b00;
parameter opcode_and = 2'b00;
parameter opcode_or  = 2'b01;
parameter opcode_or  = 2'b01;
parameter opcode_xor = 2'b10;
parameter opcode_xor = 2'b10;
input [width-1:0] a,b;
input [width-1:0] a,b;
Line 4124... Line 4719...
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
assign z = (result=={width{1'b0}});
assign z = (result=={width{1'b0}});
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
               (~a[width-1] & ~b[width-1] &  result[width-1]);
               (~a[width-1] & ~b[width-1] &  result[width-1]);
endmodule
endmodule
 
`endif
 
 
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