| Line 41... |
Line 41... |
`define FIFO_2R2W_SYNC_SIMPLEX
|
`define FIFO_2R2W_SYNC_SIMPLEX
|
`define FIFO_CMP_ASYNC
|
`define FIFO_CMP_ASYNC
|
`define FIFO_1R1W_ASYNC
|
`define FIFO_1R1W_ASYNC
|
`define FIFO_2R2W_ASYNC
|
`define FIFO_2R2W_ASYNC
|
`define FIFO_2R2W_ASYNC_SIMPLEX
|
`define FIFO_2R2W_ASYNC_SIMPLEX
|
|
`define REG_FILE
|
|
|
`define DFF
|
`define DFF
|
`define DFF_ARRAY
|
`define DFF_ARRAY
|
`define DFF_CE
|
`define DFF_CE
|
`define DFF_CE_CLEAR
|
`define DFF_CE_CLEAR
|
| Line 58... |
Line 59... |
`define DELAY
|
`define DELAY
|
`define DELAY_EMPTYFLAG
|
`define DELAY_EMPTYFLAG
|
|
|
`define WB3WB3_BRIDGE
|
`define WB3WB3_BRIDGE
|
`define WB3_ARBITER_TYPE1
|
`define WB3_ARBITER_TYPE1
|
|
`define WB_B4_ROM
|
`define WB_BOOT_ROM
|
`define WB_BOOT_ROM
|
`define WB_DPRAM
|
`define WB_DPRAM
|
|
|
`define IO_DFF_OE
|
`define IO_DFF_OE
|
`define O_DFF
|
`define O_DFF
|
| Line 218... |
Line 220... |
`endif
|
`endif
|
`ifndef DFF
|
`ifndef DFF
|
`define DFF
|
`define DFF
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
|
`ifdef REG_FILE
|
|
`ifndef DPRAM_1R1W
|
|
`define DPRAM_1R1W
|
|
`endif
|
|
`endif
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile library, clock and reset ////
|
//// Versatile library, clock and reset ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
| Line 260... |
Line 268... |
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
|
|
// Global buffer
|
|
// usage:
|
|
// use to enable global buffers for high fan out signals such as clock and reset
|
|
|
|
`ifdef ACTEL
|
`ifdef ACTEL
|
`ifdef GBUF
|
`ifdef GBUF
|
`timescale 1 ns/100 ps
|
`timescale 1 ns/100 ps
|
|
// Global buffer
|
|
// usage:
|
|
// use to enable global buffers for high fan out signals such as clock and reset
|
// Version: 8.4 8.4.0.33
|
// Version: 8.4 8.4.0.33
|
module gbuf(GL,CLK);
|
module gbuf(GL,CLK);
|
output GL;
|
output GL;
|
input CLK;
|
input CLK;
|
|
|
| Line 1023... |
Line 1030... |
`ifdef LATCH
|
`ifdef LATCH
|
`define MODULE latch
|
`define MODULE latch
|
module `BASE`MODULE ( d, le, q, clk);
|
module `BASE`MODULE ( d, le, q, clk);
|
`undef MODULE
|
`undef MODULE
|
input d, le;
|
input d, le;
|
output q;
|
input clk;
|
input clk;/*
|
always @ (le or d)
|
always @ (posedge direction_set or posedge direction_clr)
|
if le
|
if (direction_clr)
|
d <= q;
|
direction <= going_empty;
|
|
else
|
|
direction <= going_full;*/
|
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
`endif
|
`endif
|
|
|
| Line 3462... |
Line 3466... |
q <= rom[adr];
|
q <= rom[adr];
|
|
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
/*
|
|
module vl_rom ( adr, q, clk);
|
|
|
|
parameter data_width = 32;
|
|
parameter addr_width = 4;
|
|
|
|
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
|
|
{32'h18000000},
|
|
{32'hA8200000},
|
|
{32'hA8200000},
|
|
{32'hA8200000},
|
|
{32'h44003000},
|
|
{32'h15000000},
|
|
{32'h15000000},
|
|
{32'h15000000},
|
|
{32'h15000000},
|
|
{32'h15000000},
|
|
{32'h15000000},
|
|
{32'h15000000},
|
|
{32'h15000000},
|
|
{32'h15000000},
|
|
{32'h15000000},
|
|
{32'h15000000}};
|
|
|
|
input [addr_width-1:0] adr;
|
|
output reg [data_width-1:0] q;
|
|
input clk;
|
|
|
|
always @ (posedge clk)
|
|
q <= data[adr];
|
|
|
|
endmodule
|
|
*/
|
|
|
|
`ifdef RAM
|
`ifdef RAM
|
`define MODULE ram
|
`define MODULE ram
|
// Single port RAM
|
// Single port RAM
|
module `BASE`MODULE ( d, adr, we, q, clk);
|
module `BASE`MODULE ( d, adr, we, q, clk);
|
`undef MODULE
|
`undef MODULE
|
| Line 3570... |
Line 3540... |
q <= ram[adr];
|
q <= ram[adr];
|
|
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
// Dual port RAM
|
|
|
|
// ACTEL FPGA should not use logic to handle rw collision
|
|
`ifdef ACTEL
|
`ifdef ACTEL
|
|
// ACTEL FPGA should not use logic to handle rw collision
|
`define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
|
`define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
|
`else
|
`else
|
`define SYN
|
`define SYN
|
`endif
|
`endif
|
|
|
| Line 4126... |
Line 4094... |
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
|
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
|
`undef MODULE
|
`undef MODULE
|
|
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
|
`ifdef REG_FILE
|
|
`define MODULE reg_file
|
|
module `BASE`MODULE (
|
|
`undef MODULE
|
|
a1, a2, a3, wd3, we3, rd1, rd2, clk
|
|
);
|
|
parameter data_width = 32;
|
|
parameter addr_width = 5;
|
|
input [addr_width-1:0] a1, a2, a3;
|
|
input [data_width-1:0] wd3;
|
|
input we3;
|
|
output [data_width-1:0] rd1, rd2;
|
|
input clk;
|
|
|
|
`ifdef ACTEL
|
|
reg [data_width-1:0] wd3_reg;
|
|
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
|
|
reg we3_reg;
|
|
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
|
|
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
{wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
|
|
else
|
|
{wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
|
|
|
|
always @ (negedge clk)
|
|
if (we3_reg)
|
|
ram1[a3_reg] <= wd3;
|
|
always @ (posedge clk)
|
|
a1_reg <= a1;
|
|
assign rd1 = ram1[a1_reg];
|
|
|
|
always @ (negedge clk)
|
|
if (we3_reg)
|
|
ram2[a3_reg] <= wd3;
|
|
always @ (posedge clk)
|
|
a2_reg <= a2;
|
|
assign rd2 = ram2[a2_reg];
|
|
|
|
`else
|
|
|
|
`define MODULE dpram_1r1w
|
|
`BASE`MODULE
|
|
# ( .data_width(data_width), .addr_width(addr_width))
|
|
ram1 (
|
|
.d_a(wd3),
|
|
.adr_a(a3),
|
|
.we_a(we3),
|
|
.clk_a(clk),
|
|
.q_b(rd1),
|
|
.adr_b(a1),
|
|
.clk_b(clk) );
|
|
|
|
`BASE`MODULE
|
|
# ( .data_width(data_width), .addr_width(addr_width))
|
|
ram2 (
|
|
.d_a(wd3),
|
|
.adr_a(a3),
|
|
.we_a(we3),
|
|
.clk_a(clk),
|
|
.q_b(rd2),
|
|
.adr_b(a2),
|
|
.clk_b(clk) );
|
|
`undef MODULE
|
|
|
|
`endif
|
|
|
|
endmodule
|
|
`endif
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile library, wishbone stuff ////
|
//// Versatile library, wishbone stuff ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
| Line 4595... |
Line 4634... |
assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
|
assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
|
|
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
|
`ifdef WB_B4_ROM
|
|
// WB ROM
|
|
`define MODULE wb_b4_rom
|
|
module `BASE`MODULE (
|
|
`undef MODULE
|
|
wb_adr_i, wb_stb_i, wb_cyc_i,
|
|
wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
|
|
|
|
parameter dat_width = 32;
|
|
parameter dat_default = 32'h15000000;
|
|
parameter adr_width = 32;
|
|
|
|
/*
|
|
`ifndef ROM
|
|
`define ROM "rom.v"
|
|
`endif
|
|
*/
|
|
input [adr_width-1:2] wb_adr_i;
|
|
input wb_stb_i;
|
|
input wb_cyc_i;
|
|
output [dat_width-1:0] wb_dat_o;
|
|
reg [dat_width-1:0] wb_dat_o;
|
|
output wb_ack_o;
|
|
reg wb_ack_o;
|
|
output stall_o;
|
|
input wb_clk;
|
|
input wb_rst;
|
|
|
|
always @ (posedge wb_clk or posedge wb_rst)
|
|
if (wb_rst)
|
|
wb_dat_o <= {dat_width{1'b0}};
|
|
else
|
|
case (wb_adr_i[adr_width-1:2])
|
|
`ifdef ROM
|
|
`include `ROM
|
|
`endif
|
|
default:
|
|
wb_dat_o <= dat_default;
|
|
|
|
endcase // case (wb_adr_i)
|
|
|
|
|
|
always @ (posedge wb_clk or posedge wb_rst)
|
|
if (wb_rst)
|
|
wb_ack_o <= 1'b0;
|
|
else
|
|
wb_ack_o <= wb_stb_i & wb_cyc_i;
|
|
|
|
assign stall_o = 1'b0;
|
|
|
|
endmodule
|
|
`endif
|
|
|
|
|
`ifdef WB_BOOT_ROM
|
`ifdef WB_BOOT_ROM
|
// WB ROM
|
// WB ROM
|
`define MODULE wb_boot_rom
|
`define MODULE wb_boot_rom
|
module `BASE`MODULE (
|
module `BASE`MODULE (
|
`undef MODULE
|
`undef MODULE
|
| Line 4947... |
Line 5040... |
(opcode==opcode_or) ? a | b :
|
(opcode==opcode_or) ? a | b :
|
(opcode==opcode_xor) ? a ^ b :
|
(opcode==opcode_xor) ? a ^ b :
|
b;
|
b;
|
|
|
endmodule
|
endmodule
|
|
`endif
|
|
|
module vl_arith_unit ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
|
`ifdef ARITH_UNIT
|
|
`define MODULE arith_unit
|
|
module `BASE`MODULE ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
|
|
`undef MODULE
|
parameter width = 32;
|
parameter width = 32;
|
parameter opcode_add = 1'b0;
|
parameter opcode_add = 1'b0;
|
parameter opcode_sub = 1'b1;
|
parameter opcode_sub = 1'b1;
|
input [width-1:0] a,b;
|
input [width-1:0] a,b;
|
input c_in, add_sub, sign;
|
input c_in, add_sub, sign;
|
| Line 4964... |
Line 5061... |
assign ovfl = ( a[width-1] & b[width-1] & ~result[width-1]) |
|
assign ovfl = ( a[width-1] & b[width-1] & ~result[width-1]) |
|
(~a[width-1] & ~b[width-1] & result[width-1]);
|
(~a[width-1] & ~b[width-1] & result[width-1]);
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
No newline at end of file
|
No newline at end of file
|
|
`ifdef COUNT_UNIT
|
|
`define MODULE count_unit
|
|
module `BASE`MODULE (din, dout, opcode);
|
|
`undef MODULE
|
|
parameter width = 32;
|
|
input [width-1:0] din;
|
|
output [width-1:0] dout;
|
|
input opcode;
|
|
|
|
integer i;
|
|
reg [width/32+3:0] ff1, fl1;
|
|
|
|
always @(din) begin
|
|
ff1 = 0; i = 0;
|
|
while (din[i] == 0 && i < width) begin // complex condition
|
|
ff1 = ff1 + 1;
|
|
i = i + 1;
|
|
end
|
|
end
|
|
|
|
always @(din) begin
|
|
fl1 = width; i = width-1;
|
|
while (din[i] == 0 && i >= width) begin // complex condition
|
|
fl1 = fl1 - 1;
|
|
i = i - 1;
|
|
end
|
|
end
|
|
|
|
generate
|
|
if (width==32) begin
|
|
assign dout = (!opcode) ? {{58{1'b0}}, ff1} : {{58{1'b0}}, fl1};
|
|
end
|
|
endgenerate
|
|
generate
|
|
if (width==64) begin
|
|
assign dout = (!opcode) ? {{27{1'b0}}, ff1} : {{27{1'b0}}, fl1};
|
|
end
|
|
endgenerate
|
|
|
|
endmodule
|
|
`endif
|
|
|
|
`ifdef EXT_UNIT
|
|
`define MODULE ext_unit
|
|
module `BASE`MODULE ( a, b, F, result, opcode);
|
|
`undef MODULE
|
|
parameter width = 32;
|
|
input [width-1:0] a, b;
|
|
input F;
|
|
output reg [width-1:0] result;
|
|
input [2:0] opcode;
|
|
|
|
generate
|
|
if (width==32) begin
|
|
always @ (a or b or F or opcode)
|
|
begin
|
|
case (opcode)
|
|
3'b000: result = {{24{1'b0}},a[7:0]};
|
|
3'b001: result = {{24{a[7]}},a[7:0]};
|
|
3'b010: result = {{16{1'b0}},a[7:0]};
|
|
3'b011: result = {{16{a[15]}},a[15:0]};
|
|
3'b110: result = (F) ? a : b;
|
|
default: result = {b[15:0],16'h0000};
|
|
endcase
|
|
end
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (width==64) begin
|
|
always @ (a or b or F or opcode)
|
|
begin
|
|
case (opcode)
|
|
3'b000: result = {{56{1'b0}},a[7:0]};
|
|
3'b001: result = {{56{a[7]}},a[7:0]};
|
|
3'b010: result = {{48{1'b0}},a[7:0]};
|
|
3'b011: result = {{48{a[15]}},a[15:0]};
|
|
3'b110: result = (SR.F) ? a : b;
|
|
default: result = {32'h00000000,b[15:0],16'h0000};
|
|
endcase
|
|
end
|
|
end
|
|
endgenerate
|
|
endmodule
|
|
`endif
|
|
|
No newline at end of file
|
No newline at end of file
|
