Subversion Repositories versatile_library

`define WB_B3_RAM_BE

`define MODULE wb_b3_ram_be

module `BASE`MODULE (

`undef MODULE

    wb_dat_i, wb_adr_i, wb_cti_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,

    wb_dat_o, wb_ack_o, wb_clk, wb_rst);

    parameter dat_width = 32;

    parameter adr_width = 8;

input [dat_width-1:0] wb_dat_i;

input [adr_width-1:0] wb_adr_i;

input [2:0] wb_cti_i;

input [dat_width/8-1:0] wb_sel_i;

input wb_we_i, wb_stb_i, wb_cyc_i;

output [dat_width-1:0] wb_dat_o;

reg [dat_width-1:0] wb_dat_o;

output wb_stall_o;

output wb_ack_o;

reg wb_ack_o;

input wb_clk, wb_rst;

wire [dat_width/8-1:0] cke;

generate

if (dat_width==32) begin

reg [7:0] ram3 [1<<(adr_width-2)-1:0];

reg [7:0] ram2 [1<<(adr_width-2)-1:0];

reg [7:0] ram1 [1<<(adr_width-2)-1:0];

reg [7:0] ram0 [1<<(adr_width-2)-1:0];

assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};

    always @ (posedge wb_clk)

    begin

        if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];

        if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];

        if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];

        if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];

    end

    always @ (posedge wb_clk or posedge wb_rst)

    begin

        if (wb_rst)

            wb_dat_o <= 32'h0;

        else

            wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};

    end

end

endgenerate

always @ (posedge wb_clk or posedge wb_rst)

if (wb_rst)

    wb_ack_o <= 1'b0;

else

    if (wb_cti_i=3'b000 | wb_cti_i=3'b111)

        wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;

    else

        wb_ack_o <= wb_stb_i & wb_cyc_i;

endmodule

`endif

`ifdef WB_B4_RAM_BE

// WB RAM with byte enable

    end

    always @ (posedge wb_clk or posedge wb_rst)

    begin

        if (wb_rst)

            wb_dat_o <= 32'h0;

        else