URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Diff between revs 62 and 63

Rev 62	Rev 63
Line 4641...	Line 4641...

`end`	`end`
`endgenerate`	`endgenerate`

`generate`	`generate`
`for (i=0;i<nr_of_ports;i=i+1) begin`	`for (i=0;i<nr_of_ports;i=i+1) begin : spr0`
`define MODULE spr	`define MODULE spr
`BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));	`BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
`undef MODULE	`undef MODULE
`end`	`end`
`endgenerate`	`endgenerate`
Line 4698...	Line 4698...
`input [cw-1:0] wb_cti_i;`	`input [cw-1:0] wb_cti_i;`
`input [bw-1:0] wb_bte_i;`	`input [bw-1:0] wb_bte_i;`
`input [sw-1:0] wb_sel_i;`	`input [sw-1:0] wb_sel_i;`
`input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;`	`input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;`
`output [dw-1:0] wb_dat_o;`	`output [dw-1:0] wb_dat_o;`
`reg [dw-1:0] wb_dat_o;`
`output wb_ack_o;`	`output wb_ack_o;`
`reg wb_ack_o;`
`input wb_clk, wb_rst;`	`input wb_clk, wb_rst;`

`wire [sw-1:0] cke;`	`wire [sw-1:0] cke;`

`// local wb slave`	`// local wb slave`