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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Diff between revs 63 and 64

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Rev 63 Rev 64
Line 828... Line 828...
`ifdef SPR
`ifdef SPR
`define MODULE spr
`define MODULE spr
module `BASE`MODULE ( sp, r, q, clk, rst);
module `BASE`MODULE ( sp, r, q, clk, rst);
`undef MODULE
`undef MODULE
 
 
        parameter width = 1;
        //parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = 1'b0;
 
 
        input sp, r;
        input sp, r;
        output reg q;
        output reg q;
        input clk, rst;
        input clk, rst;
 
 

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