| Line 3522... |
Line 3522... |
module `BASE`MODULE ( d, adr, be, we, q, clk);
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module `BASE`MODULE ( d, adr, be, we, q, clk);
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`undef MODULE
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`undef MODULE
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parameter data_width = 32;
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parameter data_width = 32;
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parameter addr_width = 8;
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parameter addr_width = 8;
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parameter mem_size = 256;
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input [(data_width-1):0] d;
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input [(data_width-1):0] d;
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input [(addr_width-1):0] adr;
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input [(addr_width-1):0] adr;
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input [(addr_width/4)-1:0] be;
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input [(addr_width/4)-1:0] be;
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input we;
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input we;
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output reg [(data_width-1):0] q;
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output reg [(data_width-1):0] q;
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input clk;
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input clk;
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`ifdef SYSTEMVERILOG
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`ifdef SYSTEMVERILOG
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logic [data_width/8-1:0][7:0] ram[0:1<<(addr_width-2)-1];// # words = 1 << address width
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logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
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`else
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`else
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reg [data_width-1:0] ram [(1<<addr_width)-1:0];
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reg [data_width-1:0] ram [mem_size-1:0];
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`endif
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`endif
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parameter memory_init = 0;
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parameter memory_init = 0;
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parameter memory_file = "vl_ram.vmem";
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parameter memory_file = "vl_ram.vmem";
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generate if (memory_init) begin : init_mem
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generate if (memory_init) begin : init_mem
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| Line 4787... |
Line 4788... |
wb_dat_i, wb_adr_i, wb_cti_i, wb_bte_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
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wb_dat_i, wb_adr_i, wb_cti_i, wb_bte_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
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wb_dat_o, wb_ack_o, wb_clk, wb_rst);
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wb_dat_o, wb_ack_o, wb_clk, wb_rst);
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parameter nr_of_ports = 3;
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parameter nr_of_ports = 3;
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parameter wb_arbiter_type = 1;
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parameter wb_arbiter_type = 1;
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parameter adr_size = 26;
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parameter adr_size = 16;
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parameter adr_lo = 2;
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parameter adr_lo = 2;
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parameter mem_size = 1<<16;
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parameter dat_size = 32;
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parameter dat_size = 32;
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parameter memory_init = 1;
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parameter memory_init = 1;
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parameter memory_file = "vl_ram.vmem";
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parameter memory_file = "vl_ram.vmem";
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localparam aw = (adr_size - adr_lo) * nr_of_ports;
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localparam aw = (adr_size - adr_lo) * nr_of_ports;
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| Line 4874... |
Line 4876... |
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`define MODULE ram_be
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`define MODULE ram_be
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`BASE`MODULE # (
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`BASE`MODULE # (
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.data_width(dat_size),
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.data_width(dat_size),
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.addr_width(adr_size),
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.addr_width(adr_size),
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.memory_init(1),
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.memory_init(memory_init),
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.memory_file("memory_file"))
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.memory_file(memory_file))
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ram0(
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ram0(
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`undef MODULE
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`undef MODULE
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.d(wbs_dat_i),
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.d(wbs_dat_i),
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.adr(wbs_adr_i[adr_size-1:2]),
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.adr(wbs_adr_i[adr_size-1:2]),
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.be(wbs_sel_i),
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.be(wbs_sel_i),
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