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Line 4783... |
`ifdef WB_B3_RAM_BE
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`ifdef WB_B3_RAM_BE
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// WB RAM with byte enable
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// WB RAM with byte enable
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`define MODULE wb_b3_ram_be
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`define MODULE wb_b3_ram_be
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module `BASE`MODULE (
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module `BASE`MODULE (
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`undef MODULE
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`undef MODULE
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wb_dat_i, wb_adr_i, wb_cti_i, wb_bte_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
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wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
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wb_dat_o, wb_ack_o, wb_clk, wb_rst);
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wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
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parameter nr_of_ports = 3;
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parameter wb_arbiter_type = 1;
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parameter adr_size = 16;
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parameter adr_size = 16;
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parameter adr_lo = 2;
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parameter adr_lo = 2;
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parameter mem_size = 1<<16;
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parameter mem_size = 1<<16;
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parameter dat_size = 32;
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parameter dat_size = 32;
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parameter memory_init = 1;
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parameter memory_init = 1;
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parameter memory_file = "vl_ram.vmem";
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parameter memory_file = "vl_ram.vmem";
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localparam aw = (adr_size - adr_lo) * nr_of_ports;
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localparam aw = (adr_size - adr_lo);
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localparam dw = dat_size * nr_of_ports;
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localparam dw = dat_size;
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localparam sw = dat_size/8 * nr_of_ports;
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localparam sw = dat_size/8;
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localparam cw = 3 * nr_of_ports;
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localparam cw = 3;
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localparam bw = 2 * nr_of_ports;
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localparam bw = 2;
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input [dw-1:0] wb_dat_i;
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input [dw-1:0] wb_dat_i;
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input [aw-1:0] wb_adr_i;
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input [aw-1:0] wb_adr_i;
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input [cw-1:0] wb_cti_i;
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input [cw-1:0] wb_cti_i;
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input [bw-1:0] wb_bte_i;
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input [bw-1:0] wb_bte_i;
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input [sw-1:0] wb_sel_i;
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input [sw-1:0] wb_sel_i;
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input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;
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input wb_we_i, wb_stb_i, wb_cyc_i;
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output [dw-1:0] wb_dat_o;
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output [dw-1:0] wb_dat_o;
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output [nr_of_ports-1:0] wb_ack_o;
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output wb_ack_o;
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input wb_clk, wb_rst;
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input wb_clk, wb_rst;
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wire [sw-1:0] cke;
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wire [sw-1:0] cke;
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// local wb slave
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wire [dat_size-1:0] wbs_dat_i;
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wire [adr_size-1:0] wbs_adr_i;
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wire [2:0] wbs_cti_i;
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wire [1:0] wbs_bte_i;
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wire [(dat_size/8)-1:0] wbs_sel_i;
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wire wbs_we_i, wbs_stb_i, wbs_cyc_i;
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wire [dat_size-1:0] wbs_dat_o;
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reg wbs_ack_o;
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reg wbs_ack_o;
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generate
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if (nr_of_ports == 1) begin
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assign wbs_dat_i = wb_dat_i;
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assign wbs_adr_i = wb_adr_i;
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assign wbs_cti_i = wb_cti_i;
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assign wbs_sel_i = wb_sel_i;
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assign wbs_we_i = wb_we_i;
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assign wbs_stb_i = wb_stb_i;
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assign wbs_cyc_i = wb_cyc_i;
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assign wb_dat_o = wbs_dat_o;
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assign wb_ack_o = wbs_ack_o;
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end
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endgenerate
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generate
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if (nr_of_ports > 1 & wb_arbiter_type == 1) begin
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`define MODULE wb3_arbiter_type1
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`BASE`MODULE wb_arbiter0(
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`undef MODULE
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.wbm_dat_o(wb_dat_i),
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.wbm_adr_o(wb_adr_i),
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.wbm_sel_o(wb_sel_i),
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.wbm_cti_o(wb_cti_i),
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.wbm_bte_o(wb_bte_i),
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.wbm_we_o(wb_we_i),
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.wbm_stb_o(wb_stb_i),
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.wbm_cyc_o(wb_cyc_i),
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.wbm_dat_i(wb_dat_o),
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.wbm_ack_i(wb_ack_o),
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.wbm_err_i(),
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.wbm_rty_i(),
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.wbs_dat_i(wbs_dat_i),
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.wbs_adr_i(wbs_adr_i),
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.wbs_sel_i(wbs_sel_i),
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.wbs_cti_i(wbs_cti_i),
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.wbs_bte_i(wbs_bte_i),
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.wbs_we_i(wbs_we_i),
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.wbs_stb_i(wbs_stb_i),
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.wbs_cyc_i(wbs_cyc_i),
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.wbs_dat_o(wbs_dat_o),
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.wbs_ack_o(wbs_ack_o),
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.wbs_err_o(1'b0),
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.wbs_rty_o(1'b0),
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.wb_clk(wb_clk),
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.wb_rst(wb_rst)
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);
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end
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endgenerate
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`define MODULE ram_be
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`define MODULE ram_be
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`BASE`MODULE # (
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`BASE`MODULE # (
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.data_width(dat_size),
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.data_width(dat_size),
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.addr_width(adr_size),
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.addr_width(adr_size),
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.mem_size(mem_size),
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.memory_init(memory_init),
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.memory_init(memory_init),
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.memory_file(memory_file))
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.memory_file(memory_file))
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ram0(
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ram0(
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`undef MODULE
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`undef MODULE
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.d(wbs_dat_i),
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.d(wbs_dat_i),
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