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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Diff between revs 71 and 72

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Rev 71 Rev 72
Line 3521... Line 3521...
`define MODULE ram_be
`define MODULE ram_be
module `BASE`MODULE ( d, adr, be, we, q, clk);
module `BASE`MODULE ( d, adr, be, we, q, clk);
`undef MODULE
`undef MODULE
 
 
   parameter data_width = 32;
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter addr_width = 6;
   parameter mem_size = 256;
   parameter mem_size = 256;
   input [(data_width-1):0]      d;
   input [(data_width-1):0]      d;
   input [(addr_width-1):0]       adr;
   input [(addr_width-1):0]       adr;
   input [(addr_width/4)-1:0]    be;
   input [(addr_width/4)-1:0]    be;
   input                         we;
   input                         we;
Line 4816... Line 4816...
reg wbs_ack_o;
reg wbs_ack_o;
 
 
`define MODULE ram_be
`define MODULE ram_be
`BASE`MODULE # (
`BASE`MODULE # (
    .data_width(dat_size),
    .data_width(dat_size),
    .addr_width(adr_size),
    .addr_width(adr_size-2),
    .mem_size(mem_size),
    .mem_size(mem_size),
    .memory_init(memory_init),
    .memory_init(memory_init),
    .memory_file(memory_file))
    .memory_file(memory_file))
ram0(
ram0(
`undef MODULE
`undef MODULE

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