| Line 3724... |
Line 3724... |
input [(data_width/8)-1:0] be;
|
input [(data_width/8)-1:0] be;
|
input we;
|
input we;
|
output reg [(data_width-1):0] q;
|
output reg [(data_width-1):0] q;
|
input clk;
|
input clk;
|
|
|
|
|
`ifdef SYSTEMVERILOG
|
`ifdef SYSTEMVERILOG
|
logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
|
logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
|
`else
|
`else
|
reg [data_width-1:0] ram [mem_size-1:0];
|
reg [data_width-1:0] ram [mem_size-1:0];
|
|
wire [data_width/8-1:0] cke;
|
`endif
|
`endif
|
|
|
parameter memory_init = 0;
|
parameter memory_init = 0;
|
parameter memory_file = "vl_ram.vmem";
|
parameter memory_file = "vl_ram.vmem";
|
generate if (memory_init) begin : init_mem
|
generate if (memory_init) begin : init_mem
|
| Line 3747... |
Line 3749... |
//to model individual bytes within the word
|
//to model individual bytes within the word
|
|
|
always_ff@(posedge clk)
|
always_ff@(posedge clk)
|
begin
|
begin
|
if(we) begin // note: we should have a for statement to support any bus width
|
if(we) begin // note: we should have a for statement to support any bus width
|
if(be[3]) ram[adr[addr_width-2:0]][3] <= d[31:24];
|
if(be[3]) ram[adr[3] <= d[31:24];
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if(be[2]) ram[adr[addr_width-2:0]][2] <= d[23:16];
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if(be[2]) ram[adr[2] <= d[23:16];
|
if(be[1]) ram[adr[addr_width-2:0]][1] <= d[15:8];
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if(be[1]) ram[adr[1] <= d[15:8];
|
if(be[0]) ram[adr[addr_width-2:0]][0] <= d[7:0];
|
if(be[0]) ram[adr[0] <= d[7:0];
|
end
|
end
|
q <= ram[adr];
|
q <= ram[adr];
|
end
|
end
|
|
|
`else
|
`else
|
|
|
|
assign cke = {data_width/8{we}} & be;
|
genvar i;
|
genvar i;
|
generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
|
generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
|
always @ (posedge clk)
|
always @ (posedge clk)
|
if (we & be[i])
|
if (cke[i])
|
ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
|
ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
always @ (posedge clk)
|
always @ (posedge clk)
|
q <= ram[adr];
|
q <= ram[adr];
|
|
|
`endif
|
`endif
|
|
|
|
// Function to access RAM (for use by Verilator).
|
|
function [31:0] get_mem;
|
|
// verilator public
|
|
input [aw-1:0] addr;
|
|
get_mem = ram[addr];
|
|
endfunction // get_mem
|
|
|
|
// Function to write RAM (for use by Verilator).
|
|
function set_mem;
|
|
// verilator public
|
|
input [aw-1:0] addr;
|
|
input [dw-1:0] data;
|
|
ram[addr] = data;
|
|
endfunction // set_mem
|
|
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
`ifdef ACTEL
|
`ifdef ACTEL
|
// ACTEL FPGA should not use logic to handle rw collision
|
// ACTEL FPGA should not use logic to handle rw collision
|
| Line 4650... |
Line 4668... |
|
|
`ifdef WB_ADR_INC
|
`ifdef WB_ADR_INC
|
// async wb3 - wb3 bridge
|
// async wb3 - wb3 bridge
|
`timescale 1ns/1ns
|
`timescale 1ns/1ns
|
`define MODULE wb_adr_inc
|
`define MODULE wb_adr_inc
|
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, ack_o, adr_o, clk, rst);
|
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
|
`undef MODULE
|
`undef MODULE
|
parameter adr_width = 10;
|
parameter adr_width = 10;
|
parameter max_burst_width = 4;
|
parameter max_burst_width = 4;
|
input cyc_i, stb_i;
|
input cyc_i, stb_i, we_i;
|
input [2:0] cti_i;
|
input [2:0] cti_i;
|
input [1:0] bte_i;
|
input [1:0] bte_i;
|
input [adr_width-1:0] adr_i;
|
input [adr_width-1:0] adr_i;
|
output [adr_width-1:0] adr_o;
|
output [adr_width-1:0] adr_o;
|
output ack_o;
|
output ack_o;
|
| Line 4691... |
Line 4709... |
last_cycle <= (!cyc_i) ? idle :
|
last_cycle <= (!cyc_i) ? idle :
|
(cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? eoc :
|
(cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? eoc :
|
(cyc_i & !stb_i) ? ws :
|
(cyc_i & !stb_i) ? ws :
|
cyc;
|
cyc;
|
assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
|
assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
|
assign adr_o[max_burst_width-1:0] = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
|
assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
|
|
(last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] :
|
|
adr[max_burst_width-1:0];
|
assign ack_o = last_cycle == cyc;
|
assign ack_o = last_cycle == cyc;
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
generate
|
generate
|
| Line 4994... |
Line 5014... |
// wishbone slave side
|
// wishbone slave side
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
|
// avalon master side
|
// avalon master side
|
readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
|
readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
|
|
|
|
parameter linewrapburst = 1'b0;
|
|
|
input [31:0] wbs_dat_i;
|
input [31:0] wbs_dat_i;
|
input [31:2] wbs_adr_i;
|
input [31:2] wbs_adr_i;
|
input [3:0] wbs_sel_i;
|
input [3:0] wbs_sel_i;
|
input [1:0] wbs_bte_i;
|
input [1:0] wbs_bte_i;
|
input [2:0] wbs_cti_i;
|
input [2:0] wbs_cti_i;
|
| Line 5055... |
Line 5077... |
if (rst) begin
|
if (rst) begin
|
counter <= 4'd0;
|
counter <= 4'd0;
|
end else
|
end else
|
if (wbm_we_o) begin
|
if (wbm_we_o) begin
|
if (!waitrequest & !last_cyc & wbm_cyc_o) begin
|
if (!waitrequest & !last_cyc & wbm_cyc_o) begin
|
counter <= burstcount -1;
|
counter <= burstcount -4'd1;
|
end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
|
end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
|
counter <= burstcount;
|
counter <= burstcount;
|
end else if (!waitrequest & wbm_stb_o) begin
|
end else if (!waitrequest & wbm_stb_o) begin
|
counter <= counter - 4'd1;
|
counter <= counter - 4'd1;
|
end
|
end
|
| Line 5405... |
Line 5427... |
`undef MODULE
|
`undef MODULE
|
wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
|
wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
|
wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
|
wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
|
|
|
parameter adr_size = 16;
|
parameter adr_size = 16;
|
parameter adr_lo = 2;
|
parameter mem_size = 1<<adr_size;
|
parameter mem_size = 1<<16;
|
|
parameter dat_size = 32;
|
parameter dat_size = 32;
|
parameter max_burst_width = 4;
|
parameter max_burst_width = 4;
|
parameter memory_init = 1;
|
parameter memory_init = 1;
|
parameter memory_file = "vl_ram.vmem";
|
parameter memory_file = "vl_ram.vmem";
|
|
|
localparam aw = (adr_size - adr_lo);
|
localparam aw = (adr_size);
|
localparam dw = dat_size;
|
localparam dw = dat_size;
|
localparam sw = dat_size/8;
|
localparam sw = dat_size/8;
|
localparam cw = 3;
|
localparam cw = 3;
|
localparam bw = 2;
|
localparam bw = 2;
|
|
|
| Line 5427... |
Line 5448... |
input [sw-1:0] wbs_sel_i;
|
input [sw-1:0] wbs_sel_i;
|
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
|
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
|
output [dw-1:0] wbs_dat_o;
|
output [dw-1:0] wbs_dat_o;
|
output wbs_ack_o;
|
output wbs_ack_o;
|
input wb_clk, wb_rst;
|
input wb_clk, wb_rst;
|
reg wbs_ack_o;
|
|
|
|
wire [aw-1:0] adr;
|
wire [aw-1:0] adr;
|
|
|
`define MODULE ram_be
|
`define MODULE ram_be
|
`BASE`MODULE # (
|
`BASE`MODULE # (
|
| Line 5443... |
Line 5463... |
ram0(
|
ram0(
|
`undef MODULE
|
`undef MODULE
|
.d(wbs_dat_i),
|
.d(wbs_dat_i),
|
.adr(adr),
|
.adr(adr),
|
.be(wbs_sel_i),
|
.be(wbs_sel_i),
|
.we(wbs_we_i),
|
.we(wbs_we_i & wb_ack_o),
|
.q(wbs_dat_o),
|
.q(wbs_dat_o),
|
.clk(wb_clk)
|
.clk(wb_clk)
|
);
|
);
|
|
|
`define MODULE wb_adr_inc
|
`define MODULE wb_adr_inc
|
| Line 5455... |
Line 5475... |
.cyc_i(wbs_cyc_i),
|
.cyc_i(wbs_cyc_i),
|
.stb_i(wbs_stb_i),
|
.stb_i(wbs_stb_i),
|
.cti_i(wbs_cti_i),
|
.cti_i(wbs_cti_i),
|
.bte_i(wbs_bte_i),
|
.bte_i(wbs_bte_i),
|
.adr_i(wbs_adr_i),
|
.adr_i(wbs_adr_i),
|
|
.we_i(wbs_we_i),
|
.ack_o(wbs_ack_o),
|
.ack_o(wbs_ack_o),
|
.adr_o(adr),
|
.adr_o(adr),
|
.clk(wb_clk),
|
.clk(wb_clk),
|
.rst(wb_rst));
|
.rst(wb_rst));
|
`undef MODULE
|
`undef MODULE
|
