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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Diff between revs 85 and 86

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Rev 85 Rev 86
Line 3749... Line 3749...
//to model individual bytes within the word
//to model individual bytes within the word
 
 
always_ff@(posedge clk)
always_ff@(posedge clk)
begin
begin
    if(we) begin // note: we should have a for statement to support any bus width
    if(we) begin // note: we should have a for statement to support any bus width
        if(be[3]) ram[adr[3] <= d[31:24];
        if(be[3]) ram[adr][3] <= d[31:24];
        if(be[2]) ram[adr[2] <= d[23:16];
        if(be[2]) ram[adr][2] <= d[23:16];
        if(be[1]) ram[adr[1] <= d[15:8];
        if(be[1]) ram[adr][1] <= d[15:8];
        if(be[0]) ram[adr[0] <= d[7:0];
        if(be[0]) ram[adr][0] <= d[7:0];
    end
    end
    q <= ram[adr];
    q <= ram[adr];
end
end
 
 
`else
`else
Line 5463... Line 5463...
ram0(
ram0(
`undef MODULE
`undef MODULE
    .d(wbs_dat_i),
    .d(wbs_dat_i),
    .adr(adr),
    .adr(adr),
    .be(wbs_sel_i),
    .be(wbs_sel_i),
    .we(wbs_we_i & wb_ack_o),
    .we(wbs_we_i & wbs_ack_o),
    .q(wbs_dat_o),
    .q(wbs_dat_o),
    .clk(wb_clk)
    .clk(wb_clk)
);
);
 
 
`define MODULE wb_adr_inc
`define MODULE wb_adr_inc

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