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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Diff between revs 86 and 90

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Line 3711... Line 3711...
endmodule
endmodule
`endif
`endif
 
 
`ifdef RAM_BE
`ifdef RAM_BE
`define MODULE ram_be
`define MODULE ram_be
module `BASE`MODULE ( d, adr, be, we, q, clk);
module `BASE`MODULE ( d, adr, be, re, we, q, clk);
`undef MODULE
`undef MODULE
 
 
   parameter data_width = 32;
   parameter data_width = 32;
   parameter addr_width = 6;
   parameter addr_width = 6;
   parameter mem_size = 1<<addr_width;
   parameter mem_size = 1<<addr_width;
   input [(data_width-1):0]      d;
   input [(data_width-1):0]      d;
   input [(addr_width-1):0]       adr;
   input [(addr_width-1):0]       adr;
   input [(data_width/8)-1:0]    be;
   input [(data_width/8)-1:0]    be;
 
   input                         re;
   input                         we;
   input                         we;
   output reg [(data_width-1):0] q;
   output reg [(data_width-1):0] q;
   input                         clk;
   input                         clk;
 
 
 
 
Line 3754... Line 3755...
        if(be[3]) ram[adr][3] <= d[31:24];
        if(be[3]) ram[adr][3] <= d[31:24];
        if(be[2]) ram[adr][2] <= d[23:16];
        if(be[2]) ram[adr][2] <= d[23:16];
        if(be[1]) ram[adr][1] <= d[15:8];
        if(be[1]) ram[adr][1] <= d[15:8];
        if(be[0]) ram[adr][0] <= d[7:0];
        if(be[0]) ram[adr][0] <= d[7:0];
    end
    end
 
    if (re)
    q <= ram[adr];
    q <= ram[adr];
end
end
 
 
`else
`else
 
 
Line 3769... Line 3771...
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
   end
   end
   endgenerate
   endgenerate
 
 
   always @ (posedge clk)
   always @ (posedge clk)
 
    if (re)
      q <= ram[adr];
      q <= ram[adr];
 
 
`endif
`endif
 
 
   // Function to access RAM (for use by Verilator).
   // Function to access RAM (for use by Verilator).
   function [31:0] get_mem;
   function [31:0] get_mem;
      // verilator public
      // verilator public
      input [aw-1:0]             addr;
      input [addr_width-1:0]             addr;
      get_mem = ram[addr];
      get_mem = ram[addr];
   endfunction // get_mem
   endfunction // get_mem
 
 
   // Function to write RAM (for use by Verilator).
   // Function to write RAM (for use by Verilator).
   function set_mem;
   function set_mem;
      // verilator public
      // verilator public
      input [aw-1:0]             addr;
      input [addr_width-1:0]             addr;
      input [dw-1:0]             data;
      input [data_width-1:0]             data;
      ram[addr] = data;
      ram[addr] = data;
   endfunction // set_mem
   endfunction // set_mem
 
 
endmodule
endmodule
`endif
`endif
Line 4681... Line 4684...
output [adr_width-1:0] adr_o;
output [adr_width-1:0] adr_o;
output ack_o;
output ack_o;
input clk, rst;
input clk, rst;
 
 
reg [adr_width-1:0] adr;
reg [adr_width-1:0] adr;
 
wire [max_burst_width-1:0] to_adr;
 
 
generate
generate
if (max_burst_width==0) begin : inst_0
if (max_burst_width==0) begin : inst_0
    reg ack_o;
    reg ack_o;
    assign adr_o = adr_i;
    assign adr_o = adr_i;
Line 4693... Line 4697...
        ack_o <= 1'b0;
        ack_o <= 1'b0;
    else
    else
        ack_o <= cyc_i & stb_i & !ack_o;
        ack_o <= cyc_i & stb_i & !ack_o;
end else begin
end else begin
 
 
    wire [max_burst_width-1:0] to_adr;
 
 
 
    reg [1:0] last_cycle;
    reg [1:0] last_cycle;
    localparam idle = 2'b00;
    localparam idle = 2'b00;
    localparam cyc  = 2'b01;
    localparam cyc  = 2'b01;
    localparam ws   = 2'b10;
    localparam ws   = 2'b10;
    localparam eoc  = 2'b11;
    localparam eoc  = 2'b11;
Line 4712... Line 4714...
                      cyc;
                      cyc;
    assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
    assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
                                        (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] :
                                        (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] :
                                        adr[max_burst_width-1:0];
                                        adr[max_burst_width-1:0];
    assign ack_o = last_cycle == cyc;
    assign ack_o = (last_cycle==cyc | last_cycle==ws) & stb_i;
end
end
endgenerate
endgenerate
 
 
generate
generate
if (max_burst_width==2) begin : inst_2
if (max_burst_width==2) begin : inst_2
Line 5463... Line 5465...
ram0(
ram0(
`undef MODULE
`undef MODULE
    .d(wbs_dat_i),
    .d(wbs_dat_i),
    .adr(adr),
    .adr(adr),
    .be(wbs_sel_i),
    .be(wbs_sel_i),
 
    .re(wbs_stb_i),
    .we(wbs_we_i & wbs_ack_o),
    .we(wbs_we_i & wbs_ack_o),
    .q(wbs_dat_o),
    .q(wbs_dat_o),
    .clk(wb_clk)
    .clk(wb_clk)
);
);
 
 

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