| Line 8... |
Line 8... |
`ifdef ACTEL
|
`ifdef ACTEL
|
`undef SYN_KEEP
|
`undef SYN_KEEP
|
`define SYN_KEEP /*synthesis syn_keep = 1*/
|
`define SYN_KEEP /*synthesis syn_keep = 1*/
|
`endif
|
`endif
|
|
|
|
`ifdef ACTEL
|
|
// ACTEL FPGA should not use logic to handle rw collision
|
|
`define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
|
|
`else
|
|
`define SYN_NO_RW_CHECK
|
|
`endif
|
|
|
`ifdef ALL
|
`ifdef ALL
|
|
|
`define GBUF
|
`define GBUF
|
`define SYNC_RST
|
`define SYNC_RST
|
`define PLL
|
`define PLL
|
| Line 94... |
Line 101... |
`ifndef GBUF
|
`ifndef GBUF
|
`define GBUF
|
`define GBUF
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
`ifdef CDC
|
|
`ifndef PULSE2TOGGLE
|
|
`define PULSE2TOGGLE
|
|
`endif
|
|
`ifndef TOGGLE2PULSE
|
|
`define TOGGLE2PULSE
|
|
`endif
|
|
`ifndef SYNCHRONIZER
|
|
`define SYNCHRONIZER
|
|
`endif
|
|
`endif
|
|
|
|
`ifdef WB_B3_DPRAM
|
`ifdef WB_B3_DPRAM
|
`ifndef WB_ADR_INC
|
`ifndef WB_ADR_INC
|
`define WB_ADR_INC
|
`define WB_ADR_INC
|
`endif
|
`endif
|
`ifndef DPRAM_BE_2R2W
|
`ifndef DPRAM_BE_2R2W
|
| Line 167... |
Line 162... |
`define WB_ADR_INC
|
`define WB_ADR_INC
|
`endif
|
`endif
|
`ifndef dpram_be_2r2w
|
`ifndef dpram_be_2r2w
|
`define DPRAM_BE_2R2W
|
`define DPRAM_BE_2R2W
|
`endif
|
`endif
|
|
`ifndef CDC
|
|
`define CDC
|
|
`endif
|
`endif
|
`endif
|
|
|
`ifdef MULTS18X18
|
`ifdef MULTS18X18
|
`ifndef MULTS
|
`ifndef MULTS
|
`define MULTS
|
`define MULTS
|
| Line 280... |
Line 278... |
`ifndef DPRAM_1R1W
|
`ifndef DPRAM_1R1W
|
`define DPRAM_1R1W
|
`define DPRAM_1R1W
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
|
`ifdef CDC
|
|
`ifndef PULSE2TOGGLE
|
|
`define PULSE2TOGGLE
|
|
`endif
|
|
`ifndef TOGGLE2PULSE
|
|
`define TOGGLE2PULSE
|
|
`endif
|
|
`ifndef SYNCHRONIZER
|
|
`define SYNCHRONIZER
|
|
`endif
|
|
`endif
|
|
|
// size to width
|
// size to width
|
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
|
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile library, clock and reset ////
|
//// Versatile library, clock and reset ////
|
| Line 1179... |
Line 1189... |
assign emptyflag = !(|dffs);
|
assign emptyflag = !(|dffs);
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
`ifdef PULSE2TOGGLE
|
`ifdef PULSE2TOGGLE
|
`define MODULE pules2toggle
|
`define MODULE pulse2toggle
|
module `BASE`MODULE ( pl, q, clk, rst)
|
module `BASE`MODULE ( pl, q, clk, rst);
|
`undef MODULE
|
`undef MODULE
|
input pl;
|
input pl;
|
output q;
|
output reg q;
|
input clk, rst;
|
input clk, rst;
|
input
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= 1'b0;
|
q <= 1'b0;
|
else
|
else
|
q <= pl ^ q;
|
q <= pl ^ q;
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
`ifdef TOGGLE2PULSE
|
`ifdef TOGGLE2PULSE
|
`define MODULE toggle2pulse;
|
`define MODULE toggle2pulse
|
module `BASE`MODULE (d, pl, clk, rst);
|
module `BASE`MODULE (d, pl, clk, rst);
|
`undef MODULE
|
`undef MODULE
|
input d;
|
input d;
|
output pl;
|
output pl;
|
input clk, rst;
|
input clk, rst;
|
| Line 1207... |
Line 1216... |
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
dff <= 1'b0;
|
dff <= 1'b0;
|
else
|
else
|
dff <= d;
|
dff <= d;
|
assign d ^ dff;
|
assign pl = d ^ dff;
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
`ifdef SYNCHRONIZER
|
`ifdef SYNCHRONIZER
|
`define MODULE synchronizer
|
`define MODULE synchronizer
|
| Line 1266... |
Line 1275... |
.clk(clk_dst),
|
.clk(clk_dst),
|
.rst(rst_dst));
|
.rst(rst_dst));
|
|
|
// dst -> src
|
// dst -> src
|
`define MODULE pulse2toggle
|
`define MODULE pulse2toggle
|
`BASE`MODULE p2t0 (
|
`BASE`MODULE p2t1 (
|
`undef MODULE
|
`undef MODULE
|
.pl(take_it_grant_pl),
|
.pl(take_it_grant_pl),
|
.q(got_it_tg),
|
.q(got_it_tg),
|
.clk(clk_dst),
|
.clk(clk_dst),
|
.rst(rst_dst));
|
.rst(rst_dst));
|
| Line 3779... |
Line 3788... |
input [(data_width-1):0] d;
|
input [(data_width-1):0] d;
|
input [(addr_width-1):0] adr;
|
input [(addr_width-1):0] adr;
|
input we;
|
input we;
|
output reg [(data_width-1):0] q;
|
output reg [(data_width-1):0] q;
|
input clk;
|
input clk;
|
reg [data_width-1:0] ram [mem_szie-1:0];
|
reg [data_width-1:0] ram [mem_size-1:0];
|
parameter init = 0;
|
parameter init = 0;
|
parameter memory_file = "vl_ram.vmem";
|
parameter memory_file = "vl_ram.vmem";
|
generate if (init) begin : init_mem
|
generate if (init) begin : init_mem
|
initial
|
initial
|
begin
|
begin
|
| Line 3884... |
Line 3893... |
`endif
|
`endif
|
|
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
`ifdef ACTEL
|
|
// ACTEL FPGA should not use logic to handle rw collision
|
|
`define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
|
|
`else
|
|
`define SYN
|
|
`endif
|
|
|
|
`ifdef DPRAM_1R1W
|
`ifdef DPRAM_1R1W
|
`define MODULE dpram_1r1w
|
`define MODULE dpram_1r1w
|
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
|
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
|
`undef MODULE
|
`undef MODULE
|
parameter data_width = 32;
|
parameter data_width = 32;
|
| Line 3905... |
Line 3907... |
input [(addr_width-1):0] adr_b;
|
input [(addr_width-1):0] adr_b;
|
input we_a;
|
input we_a;
|
output [(data_width-1):0] q_b;
|
output [(data_width-1):0] q_b;
|
input clk_a, clk_b;
|
input clk_a, clk_b;
|
reg [(addr_width-1):0] adr_b_reg;
|
reg [(addr_width-1):0] adr_b_reg;
|
reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
|
reg [data_width-1:0] ram [mem_szie-1:0] `SYN_NO_RW_CHECK;
|
|
|
parameter init = 0;
|
parameter init = 0;
|
parameter memory_file = "vl_ram.vmem";
|
parameter memory_file = "vl_ram.vmem";
|
generate if (init) begin : init_mem
|
generate if (init) begin : init_mem
|
initial
|
initial
|
| Line 3943... |
Line 3945... |
input we_a;
|
input we_a;
|
output [(data_width-1):0] q_b;
|
output [(data_width-1):0] q_b;
|
output reg [(data_width-1):0] q_a;
|
output reg [(data_width-1):0] q_a;
|
input clk_a, clk_b;
|
input clk_a, clk_b;
|
reg [(data_width-1):0] q_b;
|
reg [(data_width-1):0] q_b;
|
reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
|
reg [data_width-1:0] ram [mem_szie-1:0] `SYN_NO_RW_CHECK;
|
|
|
parameter init = 0;
|
parameter init = 0;
|
parameter memory_file = "vl_ram.vmem";
|
parameter memory_file = "vl_ram.vmem";
|
generate if (init) begin : init_mem
|
generate if (init) begin : init_mem
|
initial
|
initial
|
| Line 3984... |
Line 3986... |
input [(data_width-1):0] d_b;
|
input [(data_width-1):0] d_b;
|
output reg [(data_width-1):0] q_a;
|
output reg [(data_width-1):0] q_a;
|
input we_b;
|
input we_b;
|
input clk_a, clk_b;
|
input clk_a, clk_b;
|
reg [(data_width-1):0] q_b;
|
reg [(data_width-1):0] q_b;
|
reg [data_width-1:0] ram [mem_size-1:0] `SYN;
|
reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
|
|
|
parameter init = 0;
|
parameter init = 0;
|
parameter memory_file = "vl_ram.vmem";
|
parameter memory_file = "vl_ram.vmem";
|
generate if (init) begin : init_mem
|
generate if (init) begin : init_mem
|
initial
|
initial
|
| Line 4046... |
Line 4048... |
//to model individual bytes within the word
|
//to model individual bytes within the word
|
|
|
generate
|
generate
|
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
|
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
|
|
|
logic [0:3][7:0] ram [0:mem_size-1];
|
logic [0:3][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
|
|
|
initial
|
initial
|
if (init)
|
if (init)
|
$readmemh(memory_file, ram);
|
$readmemh(memory_file, ram);
|
|
|
| Line 4084... |
Line 4086... |
endgenerate
|
endgenerate
|
|
|
generate
|
generate
|
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
|
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
|
|
|
logic [0:7][7:0] ram [0:mem_size-1];
|
logic [0:7][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
|
|
|
initial
|
initial
|
if (init)
|
if (init)
|
$readmemh(memory_file, ram);
|
$readmemh(memory_file, ram);
|
|
|
| Line 4189... |
Line 4191... |
end
|
end
|
endgenerate
|
endgenerate
|
|
|
`else
|
`else
|
// This modules requires SystemVerilog
|
// This modules requires SystemVerilog
|
|
// at this point anyway
|
`endif
|
`endif
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
`ifdef CAM
|
`ifdef CAM
|
| Line 4644... |
Line 4647... |
|
|
`ifdef ACTEL
|
`ifdef ACTEL
|
reg [data_width-1:0] wd3_reg;
|
reg [data_width-1:0] wd3_reg;
|
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
|
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
|
reg we3_reg;
|
reg we3_reg;
|
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
|
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
|
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
|
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
{wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
|
{wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
|
else
|
else
|
{wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
|
{wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
|
| Line 5840... |
Line 5843... |
`endif
|
`endif
|
|
|
`ifdef WBB3_WBB4_CACHE
|
`ifdef WBB3_WBB4_CACHE
|
`define MODULE wbb3_wbb4_cache
|
`define MODULE wbb3_wbb4_cache
|
module `BASE`MODULE (
|
module `BASE`MODULE (
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
|
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
|
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
|
);
|
);
|
`undef MODULE
|
`undef MODULE
|
|
|
parameter dw_s = 32;
|
parameter dw_s = 32;
|
parameter aw_s = 24;
|
parameter aw_s = 24;
|
| Line 5856... |
Line 5859... |
parameter async = 1; // wbs_clk != wbm_clk
|
parameter async = 1; // wbs_clk != wbm_clk
|
|
|
parameter nr_of_ways = 1;
|
parameter nr_of_ways = 1;
|
parameter aw_offset = 4; // 4 => 16 words per cache line
|
parameter aw_offset = 4; // 4 => 16 words per cache line
|
parameter aw_slot = 10;
|
parameter aw_slot = 10;
|
localparam aw_tag = aw_s - aw_tag_mem - aw_offset;
|
localparam aw_tag = aw_s - aw_slot - aw_offset;
|
parameter wbm_burst_size = 4; // valid options 4,8,16
|
parameter wbm_burst_size = 4; // valid options 4,8,16
|
|
localparam bte = (wbm_burst_size==4) ? 2'b01 : (wbm_burst_size==8) ? 2'b10 : 2'b11;
|
`define SIZE2WIDTH wbm_burst_size
|
`define SIZE2WIDTH wbm_burst_size
|
localparam wbm_burst_width `SIZE2WIDTH_EXPR
|
localparam wbm_burst_width `SIZE2WIDTH_EXPR
|
`undef SIZE2WIDTH
|
`undef SIZE2WIDTH
|
localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
|
localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
|
`define SIZE2WIDTH nr_of_wbm_burst
|
`define SIZE2WIDTH nr_of_wbm_burst
|
localparam nr_of_wbm_burst_width `SIZE2WIDTH_EXPR
|
localparam nr_of_wbm_burst_width `SIZE2WIDTH_EXPR
|
`undef SIZE2WIDTH
|
`undef SIZE2WIDTH
|
input [dw_s-1:0] wbs_dat_i;
|
input [dw_s-1:0] wbs_dat_i;
|
input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
|
input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
|
input [dw_s/8-1:0] wbs-sel_i;
|
input [dw_s/8-1:0] wbs_sel_i;
|
input [2:0] wbs_cti_i;
|
input [2:0] wbs_cti_i;
|
input [1:0] wbs_bte_i;
|
input [1:0] wbs_bte_i;
|
input wbs_we_i;
|
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
|
output [dw_s-1:0] wbs_dat_o;
|
output [dw_s-1:0] wbs_dat_o;
|
output wbs_ack_o;
|
output wbs_ack_o;
|
input wbs_clk, wbs_rst;
|
input wbs_clk, wbs_rst;
|
|
|
output [dw_m-1:0] wbm_dat_o;
|
output [dw_m-1:0] wbm_dat_o;
|
output [aw_m-1:0] wbm_adr_o;
|
output [aw_m-1:0] wbm_adr_o;
|
output [dw_m/8-1:0] wbm_sel_o;
|
output [dw_m/8-1:0] wbm_sel_o;
|
output [2:0] wbm_cti_o;
|
output [2:0] wbm_cti_o;
|
output [1:0] wbm_bte_o;
|
output [1:0] wbm_bte_o;
|
|
output wbm_stb_o, wbm_cyc_o, wbm_we_o;
|
input [dw_m-1:0] wbm_dat_i;
|
input [dw_m-1:0] wbm_dat_i;
|
input wbm_ack_i;
|
input wbm_ack_i;
|
input wbm_stall_i;
|
input wbm_stall_i;
|
input wbm_clk, wbm_rst;
|
input wbm_clk, wbm_rst;
|
|
|
wire dirty, valid;
|
wire dirty, valid;
|
wire [aw_tag-1:0] tag;
|
wire [aw_tag-1:0] tag;
|
wire tag_mem_we;
|
wire tag_mem_we;
|
wire [aw_tag-1:0] wbs_adr_tag;
|
wire [aw_tag-1:0] wbs_adr_tag;
|
wire [aw_slot-1:0] wbs_adr_slot;
|
wire [aw_slot-1:0] wbs_adr_slot;
|
wire [aw_offset_1:0] wbs_adr_word;
|
wire [aw_offset-1:0] wbs_adr_word;
|
wire [aw-1:0] wbs_adr;
|
wire [aw_s-1:0] wbs_adr;
|
|
|
reg [1:0] state;
|
reg [1:0] state;
|
localparam idle = 2'h0;
|
localparam idle = 2'h0;
|
localparam rdwr = 2'h1;
|
localparam rdwr = 2'h1;
|
localparam push = 2'h2;
|
localparam push = 2'h2;
|
| Line 5903... |
Line 5908... |
wire eoc;
|
wire eoc;
|
|
|
// cdc
|
// cdc
|
wire done, mem_alert, mem_done;
|
wire done, mem_alert, mem_done;
|
|
|
|
// wbm side
|
|
reg [aw_m-1:0] wbm_radr;
|
|
reg [aw_m-1:0] wbm_wadr;
|
|
wire [aw_slot+-1:0] wbm_adr;
|
|
wire wbm_radr_cke, wbm_wadr_cke;
|
|
|
|
reg [1:0] phase;
|
|
localparam wbm_wait = 2'b00;
|
|
localparam wbm_rd = 2'b10;
|
|
localparam wbm_wr = 2'b11;
|
|
|
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
|
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
|
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
|
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
|
|
|
`define MODULE ram
|
`define MODULE ram
|
`BASE`MODULE
|
`BASE`MODULE
|
# ( .data_width(aw_tag), .addr_Width(aw_slot))
|
# ( .data_width(aw_tag), .addr_width(aw_slot))
|
tag_mem ( .d(wbs_adr_slot), .adr(wbs_adr_tag), .we(done), .q(tag), .clk(wbs_clk));
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tag_mem ( .d(wbs_adr_slot), .adr(wbs_adr_tag), .we(done), .q(tag), .clk(wbs_clk));
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`undef MODULE
|
`undef MODULE
|
assign valid = wbs_adr_tag == tag;
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assign valid = wbs_adr_tag == tag;
|
|
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`define MODULE wb_adr_inc
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`define MODULE wb_adr_inc
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`BASE`MODULE # ( .adr_width(aw_slot+aw_offset), .max_burst_width(max_burst_width)) adr_inc0 (
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`BASE`MODULE # ( .adr_width(aw_s), .max_burst_width(max_burst_width)) adr_inc0 (
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.cyc_i(wbs_cyc_i),
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.cyc_i(wbs_cyc_i),
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.stb_i(wbs_stb_i & (state==idle | (state==rw & valid))), // throttle depending on valid
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.stb_i(wbs_stb_i & (state==idle | (state==rw & valid))), // throttle depending on valid
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.cti_i(wbs_cti_i),
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.cti_i(wbs_cti_i),
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.bte_i(wbs_bte_i),
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.bte_i(wbs_bte_i),
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.adr_i(wbs_adr_i),
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.adr_i(wbs_adr_i),
|
| Line 5929... |
Line 5945... |
.rst(wbsa_rst));
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.rst(wbsa_rst));
|
`undef MODULE
|
`undef MODULE
|
|
|
`define MODULE dpram_be_2r2w
|
`define MODULE dpram_be_2r2w
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`BASE`MODULE
|
`BASE`MODULE
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# ( .data_width(aw_tag), .addr_Width(aw_slot+aw_offset))
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# ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m) )
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cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr), be_a(wbs_sel_i), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .q_a(wbs_dat_o), .clk_a(wbs_clk),
|
cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]), .be_a(wbs_sel_i), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .q_a(wbs_dat_o), .clk_a(wbs_clk),
|
.d_b(wbm_dat_i), .adr_b(wbm_adr), be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
|
.d_b(wbm_dat_i), .adr_b(wbm_adr), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
|
`undef MODULE
|
`undef MODULE
|
|
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
if (wbs_rst)
|
if (wbs_rst)
|
case <= idle;
|
state <= idle;
|
else
|
else
|
case (state)
|
case (state)
|
idle:
|
idle:
|
if (wbs_cyc_i)
|
if (wbs_cyc_i)
|
state <= rdwr;
|
state <= rdwr;
|
| Line 5976... |
Line 5992... |
assign mem_alert = state==rdwr & !valid;
|
assign mem_alert = state==rdwr & !valid;
|
assign done = mem_done;
|
assign done = mem_done;
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
|
if (rst)
|
|
wbm_burst_adr <= {aw_wbm_burst{1'b0}};
|
|
else
|
|
if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i))
|
|
wbm_burst_adr <= wbm_burst_adr + (aw_wbm_burst)'d1
|
|
|
|
// FSM generating a number of burts 4 cycles
|
// FSM generating a number of burts 4 cycles
|
// actual number depends on data width ratio
|
// actual number depends on data width ratio
|
// nr_of_wbm_burst
|
// nr_of_wbm_burst
|
reg [wbm_burst_width-1:0] cnt0;
|
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0] cnt0;
|
reg [nr_of_wbm_burst_width-1:0] cnt1;
|
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0] cnt1;
|
|
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
|
if (wbm_rst)
|
|
cnt0 <= {nr_of_wbm_burst_width+wbm_burst_width{1'b0}};
|
|
else
|
|
if (wbm_radr_cke)
|
|
cnt0 <= cnt0 + 1;//(nr_of_wbm_burst_width+wbm_burst_width)1'd1;
|
|
assign wbm_radr_cke = wbm_cyc_o & wbm_stb_o & !wbm_stall_i;
|
|
assign wbm_radr = {wbs_adr_tag, tag, cnt0};
|
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
if (wbm_rst)
|
if (wbm_rst)
|
{cnt1,cnt0} <= {nr_of_wbm_burst_width+wbm_burst_width{1'b0}};
|
cnt1 <= {nr_of_wbm_burst_width+wbm_burst_width{1'b0}};
|
else
|
else
|
if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i)
|
if (wbm_wadr_cke)
|
{cnt1,cnt0} <= (nr_of_wbm_burst_width+wbm_burst_width)1'd1;
|
cnt1 <= cnt1 + 1;//(nr_of_wbm_burst_width+wbm_burst_width)1'd1;
|
|
assign wbm_wadr_cke = wbm_ack_i;
|
|
assign wbm_wadr = {wbs_adr_tag, wbs_adr_slot, cnt1};
|
|
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
|
if (wbm_rst)
|
|
phase <= wbm_wait;
|
|
else
|
|
case (phase)
|
|
wbm_wait:
|
|
if (mem_alert)
|
|
phase <= state;
|
|
wbm_wr:
|
|
if (&cnt1 & wbm_ack_i)
|
|
phase <= wbm_rd;
|
|
wbm_rd:
|
|
if (&cnt0 & wbm_ack_i)
|
|
phase <= idle;
|
|
default: phase <= wbm_wait;
|
|
endcase
|
|
|
|
assign wbm_adr_o = (phase==wbm_wr) ? {tag, wbs_adr_slot, cnt1} : {wbs_adr_tag, wbs_adr_slot, cnt1};
|
|
assign wbm_adr = (phase==wbm_wr) ? {wbs_adr_slot, cnt1} : {wbs_adr_slot, cnt1};
|
|
assign wbm_cti_o = (&cnt0 | &cnt1) ? 3'b111 : 3'b010;
|
|
assign wbm_bte_o = bte;
|
|
assign wbm_we_o = phase==wbm_wr;
|
|
|
endmodule
|
endmodule
|
`endif
|
`endif
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
