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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Diff between revs 8 and 10

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endmodule
endmodule
module dff_ce_clear ( d, ce, clear, q, clk, rst);
module dff_ce_clear ( d, ce, clear, q, clk, rst);
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = 0;
        input [width-1:0] d;
        input [width-1:0] d;
        input ce, clk, rst;
        input ce, clear, clk, rst;
        output reg [width-1:0] q;
        output reg [width-1:0] q;
        always @ (posedge clk or posedge rst)
        always @ (posedge clk or posedge rst)
        if (rst)
        if (rst)
            q <= reset_value;
            q <= reset_value;
        else
        else

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