| Line 2114... |
Line 2114... |
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
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// async wb3 - wb3 bridge
|
|
`timescale 1ns/1ns
|
`timescale 1ns/1ns
|
module vl_wb_adr_inc ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
|
module vl_wb_adr_inc ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
|
parameter adr_width = 10;
|
parameter adr_width = 10;
|
parameter max_burst_width = 4;
|
parameter max_burst_width = 4;
|
input cyc_i, stb_i, we_i;
|
input cyc_i, stb_i, we_i;
|
| Line 2727... |
Line 2726... |
assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
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assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
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assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
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assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
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assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
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assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
|
endmodule
|
endmodule
|
// WB RAM with byte enable
|
// WB RAM with byte enable
|
module vl_wb_b3_ram_be (
|
module vl_wb_ram (
|
wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
|
wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
|
wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
|
wbs_dat_o, wbs_ack_o, wbs_stall_o, wb_clk, wb_rst);
|
parameter adr_size = 16;
|
parameter adr_width = 16;
|
parameter mem_size = 1<<adr_size;
|
parameter mem_size = 1<<adr_width;
|
parameter dat_size = 32;
|
parameter dat_width = 32;
|
parameter max_burst_width = 4;
|
parameter max_burst_width = 4; // only used for B3
|
|
parameter mode = "B3"; // valid options: B3, B4
|
parameter memory_init = 1;
|
parameter memory_init = 1;
|
parameter memory_file = "vl_ram.vmem";
|
parameter memory_file = "vl_ram.vmem";
|
localparam aw = (adr_size);
|
input [dat_width-1:0] wbs_dat_i;
|
localparam dw = dat_size;
|
input [adr_width-1:0] wbs_adr_i;
|
localparam sw = dat_size/8;
|
input [2:0] wbs_cti_i;
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localparam cw = 3;
|
input [1:0] wbs_bte_i;
|
localparam bw = 2;
|
input [dat_width/8-1:0] wbs_sel_i;
|
input [dw-1:0] wbs_dat_i;
|
|
input [aw-1:0] wbs_adr_i;
|
|
input [cw-1:0] wbs_cti_i;
|
|
input [bw-1:0] wbs_bte_i;
|
|
input [sw-1:0] wbs_sel_i;
|
|
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
|
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
|
output [dw-1:0] wbs_dat_o;
|
output [dat_width-1:0] wbs_dat_o;
|
output wbs_ack_o;
|
output wbs_ack_o;
|
|
output wbs_stall_o;
|
input wb_clk, wb_rst;
|
input wb_clk, wb_rst;
|
wire [aw-1:0] adr;
|
wire [adr_width-1:0] adr;
|
vl_ram_be # (
|
wire we;
|
.data_width(dat_size),
|
generate
|
.addr_width(aw),
|
if (mode=="B3") begin : B3_inst
|
.mem_size(mem_size),
|
vl_wb_adr_inc # ( .adr_width(adr_width), .max_burst_width(max_burst_width)) adr_inc0 (
|
.memory_init(memory_init),
|
|
.memory_file(memory_file))
|
|
ram0(
|
|
.d(wbs_dat_i),
|
|
.adr(adr),
|
|
.be(wbs_sel_i),
|
|
.we(wbs_we_i & wbs_ack_o),
|
|
.q(wbs_dat_o),
|
|
.clk(wb_clk)
|
|
);
|
|
vl_wb_adr_inc # ( .adr_width(aw), .max_burst_width(max_burst_width)) adr_inc0 (
|
|
.cyc_i(wbs_cyc_i),
|
.cyc_i(wbs_cyc_i),
|
.stb_i(wbs_stb_i),
|
.stb_i(wbs_stb_i),
|
.cti_i(wbs_cti_i),
|
.cti_i(wbs_cti_i),
|
.bte_i(wbs_bte_i),
|
.bte_i(wbs_bte_i),
|
.adr_i(wbs_adr_i),
|
.adr_i(wbs_adr_i),
|
.we_i(wbs_we_i),
|
.we_i(wbs_we_i),
|
.ack_o(wbs_ack_o),
|
.ack_o(wbs_ack_o),
|
.adr_o(adr),
|
.adr_o(adr),
|
.clk(wb_clk),
|
.clk(wb_clk),
|
.rst(wb_rst));
|
.rst(wb_rst));
|
endmodule
|
assign we = wbs_we_i & wbs_ack_o;
|
// WB RAM with byte enable
|
end else if (mode=="B4") begin : B4_inst
|
module vl_wb_b4_ram_be (
|
reg wbs_ack_o_reg;
|
wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
|
always @ (posedge wb_clk or posedge wb_rst)
|
wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
|
if (wb_rst)
|
parameter dat_width = 32;
|
wbs_ack_o_reg <= 1'b0;
|
parameter adr_width = 8;
|
else
|
parameter mem_size = 1<<adr_width;
|
wbs_ack_o_reg <= wbs_stb_i & wbs_cyc_i;
|
parameter memory_init = 0;
|
assign wbs_ack_o = wbs_ack_o_reg;
|
parameter memory_file = "vl_ram.v";
|
assign wbs_stall_o = 1'b0;
|
parameter debug = 0;
|
assign adr = wbs_adr_i;
|
input [dat_width-1:0] wb_dat_i;
|
assign we = wbs_we_i & wbs_cyc_i & wbs_stb_i;
|
input [adr_width-1:0] wb_adr_i;
|
end
|
input [dat_width/8-1:0] wb_sel_i;
|
endgenerate
|
input wb_we_i, wb_stb_i, wb_cyc_i;
|
|
output [dat_width-1:0] wb_dat_o;
|
|
output wb_stall_o;
|
|
output wb_ack_o;
|
|
reg wb_ack_o;
|
|
input wb_clk, wb_rst;
|
|
wire [dat_width/8-1:0] cke;
|
|
vl_ram_be # (
|
vl_ram_be # (
|
.data_width(dat_width),
|
.data_width(dat_width),
|
.addr_width(adr_width),
|
.addr_width(adr_width),
|
.mem_size(mem_size),
|
.mem_size(mem_size),
|
.memory_init(memory_init),
|
.memory_init(memory_init),
|
.memory_file(memory_file))
|
.memory_file(memory_file))
|
ram0(
|
ram0(
|
.d(wb_dat_i),
|
.d(wbs_dat_i),
|
.adr(wb_adr_i),
|
.adr(adr),
|
.be(wb_sel_i),
|
.be(wbs_sel_i),
|
.we(wb_we_i & wb_stb_i & wb_cyc_i),
|
.we(we),
|
.q(wb_dat_o),
|
.q(wbs_dat_o),
|
.clk(wb_clk)
|
.clk(wb_clk)
|
);
|
);
|
always @ (posedge wb_clk or posedge wb_rst)
|
|
if (wb_rst)
|
|
wb_ack_o <= 1'b0;
|
|
else
|
|
wb_ack_o <= wb_stb_i & wb_cyc_i;
|
|
assign wb_stall_o = 1'b0;
|
|
endmodule
|
endmodule
|
// WB ROM
|
// WB ROM
|
module vl_wb_b4_rom (
|
module vl_wb_b4_rom (
|
wb_adr_i, wb_stb_i, wb_cyc_i,
|
wb_adr_i, wb_stb_i, wb_cyc_i,
|
wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
|
wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
|
| Line 2911... |
Line 2883... |
wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
|
wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
|
assign hit_o = hit;
|
assign hit_o = hit;
|
assign wb_dat_o = wb_dat & {32{wb_ack}};
|
assign wb_dat_o = wb_dat & {32{wb_ack}};
|
assign wb_ack_o = wb_ack;
|
assign wb_ack_o = wb_ack;
|
endmodule
|
endmodule
|
module vl_wbb3_wbb4_cache (
|
module vl_wb_cache (
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
|
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
|
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
|
);
|
);
|
parameter dw_s = 32;
|
parameter dw_s = 32;
|
parameter aw_s = 24;
|
parameter aw_s = 24;
|
| Line 3053... |
Line 3025... |
end
|
end
|
endgenerate
|
endgenerate
|
// FSM generating a number of burts 4 cycles
|
// FSM generating a number of burts 4 cycles
|
// actual number depends on data width ratio
|
// actual number depends on data width ratio
|
// nr_of_wbm_burst
|
// nr_of_wbm_burst
|
reg [wbm_burst_width-1:0] cnt_rw, cnt_ack;
|
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0] cnt_rw, cnt_ack;
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
if (wbm_rst)
|
if (wbm_rst)
|
cnt_rw <= {wbm_burst_width{1'b0}};
|
cnt_rw <= {wbm_burst_width{1'b0}};
|
else
|
else
|
if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i)
|
if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i)
|
| Line 3067... |
Line 3039... |
cnt_ack <= {wbm_burst_width{1'b0}};
|
cnt_ack <= {wbm_burst_width{1'b0}};
|
else
|
else
|
if (wbm_ack_i)
|
if (wbm_ack_i)
|
cnt_ack <= cnt_ack + 1;
|
cnt_ack <= cnt_ack + 1;
|
generate
|
generate
|
if (nr_of_wbm_burst_width==0) begin : one_burst
|
if (nr_of_wbm_burst==1) begin : one_burst
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
if (wbm_rst)
|
if (wbm_rst)
|
phase <= wbm_wait;
|
phase <= wbm_wait;
|
else
|
else
|
case (phase)
|
case (phase)
|
| Line 3093... |
Line 3065... |
wbm_rd_drain:
|
wbm_rd_drain:
|
if (&cnt_ack)
|
if (&cnt_ack)
|
phase <= wbm_wait;
|
phase <= wbm_wait;
|
default: phase <= wbm_wait;
|
default: phase <= wbm_wait;
|
endcase
|
endcase
|
assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
|
|
end else begin : multiple_burst
|
end else begin : multiple_burst
|
reg [nr_of_wbm_burst_width-1:0] cnt_burst;
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
|
if (wbm_rst)
|
|
phase <= wbm_wait;
|
|
else
|
|
case (phase)
|
|
wbm_wait:
|
|
if (mem_alert)
|
|
if (state==push)
|
|
phase <= wbm_wr;
|
|
else
|
|
phase <= wbm_rd;
|
|
wbm_wr:
|
|
if (&cnt_rw[wbm_burst_width-1:0])
|
|
phase <= wbm_wr_drain;
|
|
wbm_wr_drain:
|
|
if (&cnt_ack)
|
|
phase <= wbm_rd;
|
|
else if (&cnt_ack[wbm_burst_width-1:0])
|
|
phase <= wbm_wr;
|
|
wbm_rd:
|
|
if (&cnt_rw[wbm_burst_width-1:0])
|
|
phase <= wbm_rd_drain;
|
|
wbm_rd_drain:
|
|
if (&cnt_ack)
|
|
phase <= wbm_wait;
|
|
else if (&cnt_ack[wbm_burst_width-1:0])
|
|
phase <= wbm_rd;
|
|
default: phase <= wbm_wait;
|
|
endcase
|
end
|
end
|
endgenerate
|
endgenerate
|
|
assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
|
assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
|
assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
|
assign wbm_adr = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_rw};
|
assign wbm_adr = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_rw};
|
assign wbm_sel_o = {dw_m/8{1'b1}};
|
assign wbm_sel_o = {dw_m/8{1'b1}};
|
assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
|
assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
|
assign wbm_bte_o = bte;
|
assign wbm_bte_o = bte;
|
