Line 1193... |
Line 1193... |
q <= {1'b1,{length-1{1'b0}}};
|
q <= {1'b1,{length-1{1'b0}}};
|
else
|
else
|
if (cke)
|
if (cke)
|
q <= {q[length-1],q[0:length-2]};
|
q <= {q[length-1],q[0:length-2]};
|
endmodule
|
endmodule
|
|
module vl_cnt_shreg_clear ( clear, q, rst, clk);
|
|
parameter length = 4;
|
|
input clear;
|
|
output reg [0:length-1] q;
|
|
input rst;
|
|
input clk;
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
q <= {1'b1,{length-1{1'b0}}};
|
|
else
|
|
if (clear)
|
|
q <= {1'b1,{length-1{1'b0}}};
|
|
else
|
|
q <= q >> 1;
|
|
endmodule
|
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
|
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
|
parameter length = 4;
|
parameter length = 4;
|
input cke, clear;
|
input cke, clear;
|
output reg [0:length-1] q;
|
output reg [0:length-1] q;
|
input rst;
|
input rst;
|
Line 2497... |
Line 2512... |
.wbm_dat_i(readdata),
|
.wbm_dat_i(readdata),
|
.wbm_ack_i(wbm_ack_i),
|
.wbm_ack_i(wbm_ack_i),
|
.wbm_clk(clk),
|
.wbm_clk(clk),
|
.wbm_rst(rst));
|
.wbm_rst(rst));
|
endmodule
|
endmodule
|
module vl_wb3_arbiter_type1 (
|
|
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
|
|
wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
|
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
|
|
wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
|
|
wb_clk, wb_rst
|
|
);
|
|
parameter nr_of_ports = 3;
|
|
parameter adr_size = 26;
|
|
parameter adr_lo = 2;
|
|
parameter dat_size = 32;
|
|
parameter sel_size = dat_size/8;
|
|
localparam aw = (adr_size - adr_lo) * nr_of_ports;
|
|
localparam dw = dat_size * nr_of_ports;
|
|
localparam sw = sel_size * nr_of_ports;
|
|
localparam cw = 3 * nr_of_ports;
|
|
localparam bw = 2 * nr_of_ports;
|
|
input [dw-1:0] wbm_dat_o;
|
|
input [aw-1:0] wbm_adr_o;
|
|
input [sw-1:0] wbm_sel_o;
|
|
input [cw-1:0] wbm_cti_o;
|
|
input [bw-1:0] wbm_bte_o;
|
|
input [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
|
|
output [dw-1:0] wbm_dat_i;
|
|
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
|
|
output [dat_size-1:0] wbs_dat_i;
|
|
output [adr_size-1:adr_lo] wbs_adr_i;
|
|
output [sel_size-1:0] wbs_sel_i;
|
|
output [2:0] wbs_cti_i;
|
|
output [1:0] wbs_bte_i;
|
|
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
|
|
input [dat_size-1:0] wbs_dat_o;
|
|
input wbs_ack_o, wbs_err_o, wbs_rty_o;
|
|
input wb_clk, wb_rst;
|
|
reg [nr_of_ports-1:0] select;
|
|
wire [nr_of_ports-1:0] state;
|
|
wire [nr_of_ports-1:0] eoc; // end-of-cycle
|
|
wire [nr_of_ports-1:0] sel;
|
|
wire idle;
|
|
genvar i;
|
|
assign idle = !(|state);
|
|
generate
|
|
if (nr_of_ports == 2) begin
|
|
wire [2:0] wbm1_cti_o, wbm0_cti_o;
|
|
assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
|
//assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
|
always @ (idle or wbm_cyc_o)
|
|
if (idle)
|
|
casex (wbm_cyc_o)
|
|
2'b1x : select = 2'b10;
|
|
2'b01 : select = 2'b01;
|
|
default : select = {nr_of_ports{1'b0}};
|
|
endcase
|
|
else
|
|
select = {nr_of_ports{1'b0}};
|
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
|
end
|
|
endgenerate
|
|
generate
|
|
if (nr_of_ports == 3) begin
|
|
wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
|
|
assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
|
always @ (idle or wbm_cyc_o)
|
|
if (idle)
|
|
casex (wbm_cyc_o)
|
|
3'b1xx : select = 3'b100;
|
|
3'b01x : select = 3'b010;
|
|
3'b001 : select = 3'b001;
|
|
default : select = {nr_of_ports{1'b0}};
|
|
endcase
|
|
else
|
|
select = {nr_of_ports{1'b0}};
|
|
// assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
|
assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
|
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
|
end
|
|
endgenerate
|
|
generate
|
|
if (nr_of_ports == 4) begin
|
|
wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
|
|
assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
|
//assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
|
always @ (idle or wbm_cyc_o)
|
|
if (idle)
|
|
casex (wbm_cyc_o)
|
|
4'b1xxx : select = 4'b1000;
|
|
4'b01xx : select = 4'b0100;
|
|
4'b001x : select = 4'b0010;
|
|
4'b0001 : select = 4'b0001;
|
|
default : select = {nr_of_ports{1'b0}};
|
|
endcase
|
|
else
|
|
select = {nr_of_ports{1'b0}};
|
|
assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
|
|
assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
|
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
|
end
|
|
endgenerate
|
|
generate
|
|
if (nr_of_ports == 5) begin
|
|
wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
|
|
assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
|
//assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
|
always @ (idle or wbm_cyc_o)
|
|
if (idle)
|
|
casex (wbm_cyc_o)
|
|
5'b1xxxx : select = 5'b10000;
|
|
5'b01xxx : select = 5'b01000;
|
|
5'b001xx : select = 5'b00100;
|
|
5'b0001x : select = 5'b00010;
|
|
5'b00001 : select = 5'b00001;
|
|
default : select = {nr_of_ports{1'b0}};
|
|
endcase
|
|
else
|
|
select = {nr_of_ports{1'b0}};
|
|
assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
|
|
assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
|
|
assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
|
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
|
end
|
|
endgenerate
|
|
generate
|
|
if (nr_of_ports == 6) begin
|
|
wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
|
|
assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
|
//assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
|
always @ (idle or wbm_cyc_o)
|
|
if (idle)
|
|
casex (wbm_cyc_o)
|
|
6'b1xxxxx : select = 6'b100000;
|
|
6'b01xxxx : select = 6'b010000;
|
|
6'b001xxx : select = 6'b001000;
|
|
6'b0001xx : select = 6'b000100;
|
|
6'b00001x : select = 6'b000010;
|
|
6'b000001 : select = 6'b000001;
|
|
default : select = {nr_of_ports{1'b0}};
|
|
endcase
|
|
else
|
|
select = {nr_of_ports{1'b0}};
|
|
assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
|
|
assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
|
|
assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
|
|
assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
|
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
|
end
|
|
endgenerate
|
|
generate
|
|
if (nr_of_ports == 7) begin
|
|
wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
|
|
assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
|
//assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
|
always @ (idle or wbm_cyc_o)
|
|
if (idle)
|
|
casex (wbm_cyc_o)
|
|
7'b1xxxxxx : select = 7'b1000000;
|
|
7'b01xxxxx : select = 7'b0100000;
|
|
7'b001xxxx : select = 7'b0010000;
|
|
7'b0001xxx : select = 7'b0001000;
|
|
7'b00001xx : select = 7'b0000100;
|
|
7'b000001x : select = 7'b0000010;
|
|
7'b0000001 : select = 7'b0000001;
|
|
default : select = {nr_of_ports{1'b0}};
|
|
endcase
|
|
else
|
|
select = {nr_of_ports{1'b0}};
|
|
assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
|
|
assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
|
|
assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
|
|
assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
|
|
assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
|
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
|
end
|
|
endgenerate
|
|
generate
|
|
if (nr_of_ports == 8) begin
|
|
wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
|
|
assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
|
//assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
|
always @ (idle or wbm_cyc_o)
|
|
if (idle)
|
|
casex (wbm_cyc_o)
|
|
8'b1xxxxxxx : select = 8'b10000000;
|
|
8'b01xxxxxx : select = 8'b01000000;
|
|
8'b001xxxxx : select = 8'b00100000;
|
|
8'b0001xxxx : select = 8'b00010000;
|
|
8'b00001xxx : select = 8'b00001000;
|
|
8'b000001xx : select = 8'b00000100;
|
|
8'b0000001x : select = 8'b00000010;
|
|
8'b00000001 : select = 8'b00000001;
|
|
default : select = {nr_of_ports{1'b0}};
|
|
endcase
|
|
else
|
|
select = {nr_of_ports{1'b0}};
|
|
assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
|
|
assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
|
|
assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
|
|
assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
|
|
assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
|
|
assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
|
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
|
end
|
|
endgenerate
|
|
generate
|
|
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
|
|
vl_spr sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
|
|
end
|
|
endgenerate
|
|
assign sel = select | state;
|
|
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
|
|
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
|
|
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
|
|
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
|
|
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
|
|
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
|
|
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
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assign wbs_cyc_i = |sel;
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assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
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assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
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assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
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assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
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endmodule
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// WB RAM with byte enable
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// WB RAM with byte enable
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module vl_wb_ram (
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module vl_wb_ram (
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wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
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wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
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wbs_dat_o, wbs_ack_o, wbs_stall_o, wb_clk, wb_rst);
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wbs_dat_o, wbs_ack_o, wbs_stall_o, wb_clk, wb_rst);
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parameter adr_width = 16;
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parameter adr_width = 16;
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