URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Diff between revs 109 and 110

Rev 109	Rev 110
Line 2818...	Line 2818...
`assign wbsb_stall_o = 1'b0;`	`assign wbsb_stall_o = 1'b0;`
`assign we_b = wbsb_we_i & wbsb_cyc_i & wbsb_stb_i;`	`assign we_b = wbsb_we_i & wbsb_cyc_i & wbsb_stb_i;`
`end`	`end`
`endgenerate`	`endgenerate`
`vl_dpram_be_2r2w # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size),`	`vl_dpram_be_2r2w # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size),`
`.b_data_width(data_width_b), .b_addr_width(addr_width_b),`	`.b_data_width(data_width_b),`
`.memory_init(memory_init), .memory_file(memory_file))`	`.memory_init(memory_init), .memory_file(memory_file))`
`ram_i (`	`ram_i (`
`.d_a(wbsa_dat_i),`	`.d_a(wbsa_dat_i),`
`.q_a(wbsa_dat_o),`	`.q_a(wbsa_dat_o),`
`.adr_a(adr_a),`	`.adr_a(adr_a),`