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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Diff between revs 111 and 116

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Rev 111 Rev 116
Line 419... Line 419...
assign pl = d ^ dff;
assign pl = d ^ dff;
endmodule
endmodule
module vl_synchronizer (d, q, clk, rst);
module vl_synchronizer (d, q, clk, rst);
input d;
input d;
output reg q;
output reg q;
output clk, rst;
input clk, rst;
reg dff;
reg dff;
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
if (rst)
if (rst)
    {q,dff} <= 2'b00;
    {q,dff} <= 2'b00;
else
else

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