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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Diff between revs 118 and 119

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Rev 118 Rev 119
Line 1417... Line 1417...
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   input                         we_a;
   output reg [(data_width-1):0]          q_b;
   output reg [(data_width-1):0]          q_b;
   input                         clk_a, clk_b;
   input                         clk_a, clk_b;
   reg [data_width-1:0] ram [mem_size-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [data_width-1:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
    parameter memory_init = 0;
    parameter memory_init = 0;
    parameter memory_file = "vl_ram.vmem";
    parameter memory_file = "vl_ram.vmem";
    parameter debug = 0;
    parameter debug = 0;
    generate
    generate
    if (memory_init == 1) begin : init_mem
    if (memory_init == 1) begin : init_mem
Line 1457... Line 1457...
   input                         we_a;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   output [(data_width-1):0]      q_b;
   output reg [(data_width-1):0] q_a;
   output reg [(data_width-1):0] q_a;
   input                         clk_a, clk_b;
   input                         clk_a, clk_b;
   reg [(data_width-1):0]         q_b;
   reg [(data_width-1):0]         q_b;
   reg [data_width-1:0] ram [mem_size-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [data_width-1:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
    parameter memory_init = 0;
    parameter memory_init = 0;
    parameter memory_file = "vl_ram.vmem";
    parameter memory_file = "vl_ram.vmem";
    parameter debug = 0;
    parameter debug = 0;
    generate
    generate
    if (memory_init == 1) begin : init_mem
    if (memory_init == 1) begin : init_mem
Line 1501... Line 1501...
   input [(data_width-1):0]       d_b;
   input [(data_width-1):0]       d_b;
   output reg [(data_width-1):0] q_a;
   output reg [(data_width-1):0] q_a;
   input                         we_b;
   input                         we_b;
   input                         clk_a, clk_b;
   input                         clk_a, clk_b;
   reg [(data_width-1):0]         q_b;
   reg [(data_width-1):0]         q_b;
   reg [data_width-1:0] ram [mem_size-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [data_width-1:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
    parameter memory_init = 0;
    parameter memory_init = 0;
    parameter memory_file = "vl_ram.vmem";
    parameter memory_file = "vl_ram.vmem";
    parameter debug = 0;
    parameter debug = 0;
    generate
    generate
    if (memory_init == 1) begin : init_mem
    if (memory_init == 1) begin : init_mem
Line 1552... Line 1552...
   input [(data_width-1):0]       d_b;
   input [(data_width-1):0]       d_b;
   output reg [(data_width-1):0] q_a;
   output reg [(data_width-1):0] q_a;
   input                         we_b;
   input                         we_b;
   input                         clk_a, clk_b;
   input                         clk_a, clk_b;
   reg [(data_width-1):0]         q_b;
   reg [(data_width-1):0]         q_b;
   reg [data_width-1:0] ram [mem_size-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [data_width-1:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
    parameter memory_init = 0;
    parameter memory_init = 0;
    parameter memory_file = "vl_ram.vmem";
    parameter memory_file = "vl_ram.vmem";
    parameter debug = 0;
    parameter debug = 0;
    generate
    generate
    if (memory_init) begin : init_mem
    if (memory_init) begin : init_mem

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