| Line 1417... |
Line 1417... |
input [(addr_width-1):0] adr_a;
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input [(addr_width-1):0] adr_a;
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input [(addr_width-1):0] adr_b;
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input [(addr_width-1):0] adr_b;
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input we_a;
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input we_a;
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output reg [(data_width-1):0] q_b;
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output reg [(data_width-1):0] q_b;
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input clk_a, clk_b;
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input clk_a, clk_b;
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reg [data_width-1:0] ram [mem_size-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [data_width-1:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
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parameter memory_init = 0;
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parameter memory_init = 0;
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parameter memory_file = "vl_ram.vmem";
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parameter memory_file = "vl_ram.vmem";
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parameter debug = 0;
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parameter debug = 0;
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generate
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generate
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if (memory_init == 1) begin : init_mem
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if (memory_init == 1) begin : init_mem
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| Line 1457... |
Line 1457... |
input we_a;
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input we_a;
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output [(data_width-1):0] q_b;
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output [(data_width-1):0] q_b;
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output reg [(data_width-1):0] q_a;
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output reg [(data_width-1):0] q_a;
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input clk_a, clk_b;
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input clk_a, clk_b;
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reg [(data_width-1):0] q_b;
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reg [(data_width-1):0] q_b;
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reg [data_width-1:0] ram [mem_size-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [data_width-1:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
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parameter memory_init = 0;
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parameter memory_init = 0;
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parameter memory_file = "vl_ram.vmem";
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parameter memory_file = "vl_ram.vmem";
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parameter debug = 0;
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parameter debug = 0;
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generate
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generate
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if (memory_init == 1) begin : init_mem
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if (memory_init == 1) begin : init_mem
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| Line 1501... |
Line 1501... |
input [(data_width-1):0] d_b;
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input [(data_width-1):0] d_b;
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output reg [(data_width-1):0] q_a;
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output reg [(data_width-1):0] q_a;
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input we_b;
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input we_b;
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input clk_a, clk_b;
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input clk_a, clk_b;
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reg [(data_width-1):0] q_b;
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reg [(data_width-1):0] q_b;
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reg [data_width-1:0] ram [mem_size-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [data_width-1:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
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parameter memory_init = 0;
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parameter memory_init = 0;
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parameter memory_file = "vl_ram.vmem";
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parameter memory_file = "vl_ram.vmem";
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parameter debug = 0;
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parameter debug = 0;
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generate
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generate
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if (memory_init == 1) begin : init_mem
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if (memory_init == 1) begin : init_mem
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| Line 1552... |
Line 1552... |
input [(data_width-1):0] d_b;
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input [(data_width-1):0] d_b;
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output reg [(data_width-1):0] q_a;
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output reg [(data_width-1):0] q_a;
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input we_b;
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input we_b;
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input clk_a, clk_b;
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input clk_a, clk_b;
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reg [(data_width-1):0] q_b;
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reg [(data_width-1):0] q_b;
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reg [data_width-1:0] ram [mem_size-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [data_width-1:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
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parameter memory_init = 0;
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parameter memory_init = 0;
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parameter memory_file = "vl_ram.vmem";
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parameter memory_file = "vl_ram.vmem";
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parameter debug = 0;
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parameter debug = 0;
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generate
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generate
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if (memory_init) begin : init_mem
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if (memory_init) begin : init_mem
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