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endmodule
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endmodule
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module vl_dpram_be_2r2w ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
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module vl_dpram_be_2r2w ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
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parameter a_data_width = 32;
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parameter a_data_width = 32;
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parameter a_addr_width = 8;
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parameter a_addr_width = 8;
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parameter b_data_width = 64; //a_data_width;
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parameter b_data_width = 64; //a_data_width;
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localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
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//localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
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localparam b_addr_width =
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(a_data_width==b_data_width) ? aw_m :
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(a_data_width==b_data_width*2) ? aw_m+1 :
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(a_data_width==b_data_width*4) ? aw_m+2 :
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(a_data_width==b_data_width*8) ? aw_m+3 :
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(a_data_width==b_data_width*16) ? aw_m+4 :
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(a_data_width==b_data_width*32) ? aw_m+5 :
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(a_data_width==b_data_width/2) ? aw_m-1 :
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(a_data_width==b_data_width/4) ? aw_m-2 :
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(a_data_width==b_data_width/8) ? aw_m-3 :
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(a_data_width==b_data_width/16) ? aw_m-4 :
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(a_data_width==b_data_width/32) ? aw_m-5 : 0;
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localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
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localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
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parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
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parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
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parameter memory_init = 0;
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parameter memory_init = 0;
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parameter memory_file = "vl_ram.vmem";
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parameter memory_file = "vl_ram.vmem";
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parameter debug = 0;
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parameter debug = 0;
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wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
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wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
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);
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);
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parameter dw_s = 32;
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parameter dw_s = 32;
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parameter aw_s = 24;
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parameter aw_s = 24;
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parameter dw_m = dw_s;
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parameter dw_m = dw_s;
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localparam aw_m = dw_s * aw_s / dw_m;
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//localparam aw_m = dw_s * aw_s / dw_m;
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localparam aw_m =
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(dw_s==dw_m) ? aw_m :
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(dw_s==dw_m*2) ? aw_m+1 :
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(dw_s==dw_m*4) ? aw_m+2 :
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(dw_s==dw_m*8) ? aw_m+3 :
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(dw_s==dw_m*16) ? aw_m+4 :
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(dw_s==dw_m*32) ? aw_m+5 :
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(dw_s==dw_m/2) ? aw_m-1 :
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(dw_s==adw_m/4) ? aw_m-2 :
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(dw_s==dw_m/8) ? aw_m-3 :
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(dw_s==dw_m/16) ? aw_m-4 :
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(dw_s==dw_m/32) ? aw_m-5 : 0;
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parameter wbs_max_burst_width = 4;
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parameter wbs_max_burst_width = 4;
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parameter wbs_mode = "B3";
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parameter wbs_mode = "B3";
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parameter async = 1; // wbs_clk != wbm_clk
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parameter async = 1; // wbs_clk != wbm_clk
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parameter nr_of_ways = 1;
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parameter nr_of_ways = 1;
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parameter aw_offset = 4; // 4 => 16 words per cache line
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parameter aw_offset = 4; // 4 => 16 words per cache line
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