| Line 1763... |
Line 1763... |
parameter wbs_adr = 1'b0;
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parameter wbs_adr = 1'b0;
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parameter wbs_data = 1'b1;
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parameter wbs_data = 1'b1;
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parameter wbm_adr0 = 2'b00;
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parameter wbm_adr0 = 2'b00;
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parameter wbm_adr1 = 2'b01;
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parameter wbm_adr1 = 2'b01;
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parameter wbm_data = 2'b10;
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parameter wbm_data = 2'b10;
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reg wbs_we_reg;
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reg [1:0] wbs_bte_reg;
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reg [1:0] wbs_bte_reg;
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reg wbs;
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reg wbs;
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wire wbs_eoc_alert, wbm_eoc_alert;
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wire wbs_eoc_alert, wbm_eoc_alert;
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reg wbs_eoc, wbm_eoc;
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reg wbs_eoc, wbm_eoc;
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reg [1:0] wbm;
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reg [1:0] wbm;
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reg [1:16] wbs_count, wbm_count;
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reg [1:16] wbs_count, wbm_count;
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reg wbs_ack_o_rd;
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wire wbs_ack_o_wr;
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wire [35:0] a_d, a_q, b_d, b_q;
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wire [35:0] a_d, a_q, b_d, b_q;
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wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
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wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
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reg a_rd_reg;
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reg a_rd_reg;
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wire b_rd_adr, b_rd_data;
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wire b_rd_adr, b_rd_data;
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reg b_rd_data_reg;
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reg b_rd_data_reg;
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| Line 1817... |
Line 1814... |
a_rd_reg <= a_rd;
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a_rd_reg <= a_rd;
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assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
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assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
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assign wbs_dat_o = a_q[35:4];
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assign wbs_dat_o = a_q[35:4];
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always @ (posedge wbs_clk or posedge wbs_rst)
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always @ (posedge wbs_clk or posedge wbs_rst)
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if (wbs_rst)
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if (wbs_rst)
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{wbs_we_reg,wbs_bte_reg} <= {1'b0,2'b00};
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wbs_bte_reg <= 2'b00;
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else
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else
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{wbs_we_reg,wbs_bte_reg} <= {wbs_we_i,wbs_bte_i};
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wbs_bte_reg <= wbs_bte_i;
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// wbm FIFO
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// wbm FIFO
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assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
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assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
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always @ (posedge wbm_clk or posedge wbm_rst)
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always @ (posedge wbm_clk or posedge wbm_rst)
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if (wbm_rst)
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if (wbm_rst)
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wbm_eoc <= 1'b0;
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wbm_eoc <= 1'b0;
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