URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Diff between revs 131 and 132

Rev 131	Rev 132
Line 2980...	Line 2980...
`(dw_s==dw_m*8) ? aw_slot+aw_offset-3 :`	`(dw_s==dw_m*8) ? aw_slot+aw_offset-3 :`
`(dw_s==dw_m*16) ? aw_slot+aw_offset-4 : 0;`	`(dw_s==dw_m*16) ? aw_slot+aw_offset-4 : 0;`
`vl_dpram_be_2r2w`	`vl_dpram_be_2r2w`
`# ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))`	`# ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))`
`cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]), .be_a(wbs_sel_i), .we_a(we), .q_a(wbs_dat_o), .clk_a(wbs_clk),`	`cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]), .be_a(wbs_sel_i), .we_a(we), .q_a(wbs_dat_o), .clk_a(wbs_clk),`
`.d_b(wbm_dat_i), .adr_b(wbm_adr_o[aw_slot+aw_offset-1:0]), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));`	`.d_b(wbm_dat_i), .adr_b(wbm_adr_o[cache_mem_b_aw-1:0]), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));`
`always @ (posedge wbs_clk or posedge wbs_rst)`	`always @ (posedge wbs_clk or posedge wbs_rst)`
`if (wbs_rst)`	`if (wbs_rst)`
`state <= idle;`	`state <= idle;`
`else`	`else`
`case (state)`	`case (state)`