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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Diff between revs 136 and 137

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Rev 136 Rev 137
Line 1871... Line 1871...
    .we_a(we_a),
    .we_a(we_a),
    .clk_a(clk_a),
    .clk_a(clk_a),
    .d_b({d_b,d_b}),
    .d_b({d_b,d_b}),
    .q_b(temp),
    .q_b(temp),
    .adr_b(adr_b[b_addr_width-1:1]),
    .adr_b(adr_b[b_addr_width-1:1]),
    .be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
    .be_b({be_b,be_b} & {{2{!adr_b[0]}},{2{adr_b[0]}}}),
    .we_b(we_b),
    .we_b(we_b),
    .clk_b(clk_b)
    .clk_b(clk_b)
);
);
always @ (adr_b[0] or temp)
always @ (adr_b[0] or temp)
    if (adr_b[0])
    if (adr_b[0])
Line 3062... Line 3062...
// cdc
// cdc
wire done, mem_alert, mem_done;
wire done, mem_alert, mem_done;
// wbm side
// wbm side
reg [aw_m-1:0] wbm_radr;
reg [aw_m-1:0] wbm_radr;
reg [aw_m-1:0] wbm_wadr;
reg [aw_m-1:0] wbm_wadr;
wire [aw_slot-1:0] wbm_adr;
//wire [aw_slot-1:0] wbm_adr;
 
wire [aw_m-1:0] wbm_adr;
wire wbm_radr_cke, wbm_wadr_cke;
wire wbm_radr_cke, wbm_wadr_cke;
reg [2:0] phase;
reg [2:0] phase;
// phase = {we,stb,cyc}
// phase = {we,stb,cyc}
localparam wbm_wait     = 3'b000;
localparam wbm_wait     = 3'b000;
localparam wbm_wr       = 3'b111;
localparam wbm_wr       = 3'b111;
Line 3234... Line 3235...
    endcase
    endcase
end
end
endgenerate
endgenerate
assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
assign wbm_adr   = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_rw};
assign wbm_adr   = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_ack};
assign wbm_sel_o = {dw_m/8{1'b1}};
assign wbm_sel_o = {dw_m/8{1'b1}};
assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
assign wbm_bte_o = bte;
assign wbm_bte_o = bte;
assign {wbm_we_o, wbm_stb_o, wbm_cyc_o}  = phase;
assign {wbm_we_o, wbm_stb_o, wbm_cyc_o}  = phase;
endmodule
endmodule

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