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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Diff between revs 144 and 145

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Rev 144 Rev 145
Line 3408... Line 3408...
input clk;
input clk;
generate
generate
if (debug==1) begin : debug_we
if (debug==1) begin : debug_we
    always @ (posedge clk)
    always @ (posedge clk)
        if (we3)
        if (we3)
            $display ("Value %h written at register %h : time %t", d, adr, $time);
            $display ("Value %h written at register %h : time %t", wd3, a3, $time);
end
end
endgenerate
endgenerate
reg [data_width-1:0] wd3_reg;
reg [data_width-1:0] wd3_reg;
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
reg we3_reg;
reg we3_reg;

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