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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Diff between revs 149 and 150

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Rev 149 Rev 150
Line 5179... Line 5179...
always @ (din or s or opcode)
always @ (din or s or opcode)
`endif
`endif
    case (opcode)
    case (opcode)
    opcode_sll: dout = din << s;
    opcode_sll: dout = din << s;
    opcode_srl: dout = din >> s;
    opcode_srl: dout = din >> s;
    opcode_sra: dout = (din >> s) | ({32,din[31]}} << (6'd32-{1'b0,s}}));
    opcode_sra: dout = (din >> s) | ({32,din[31]}} << (6'd32-{1'b0,s}));
    //opcode_ror: dout = not yet implemented
    //opcode_ror: dout = not yet implemented
    default: dout = din << s;
    default: dout = din << s;
    endcase
    endcase
end
end
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