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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Diff between revs 152 and 153

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Rev 152 Rev 153
Line 5170... Line 5170...
                     (sll) ?  {8{1'b0}}:
                     (sll) ?  {8{1'b0}}:
                     (s[4:3]==2'b01) ? tmp[1] :
                     (s[4:3]==2'b01) ? tmp[1] :
                     (s[4:3]==2'b10) ? tmp[2] :
                     (s[4:3]==2'b10) ? tmp[2] :
                     tmp[3];
                     tmp[3];
end else begin : impl_classic
end else begin : impl_classic
reg [31:0] dout;
assign dout =
`ifdef SYSTEMVERILOG
    (opcode==opcode_sll) ? din << s :
always_comb
    (opcode==opcode_srl) ? din >> s :
`else
    (opcode==opcode_sra) ? (din >> s) | ({32{din[31]}} << (6'd32-{1'b0,s})) :
always @ (din or s or opcode)
    din << s;
`endif
 
    case (opcode)
 
    opcode_sll: dout = din << s;
 
    opcode_srl: dout = din >> s;
 
    opcode_sra: dout = (din >> s) | ({32{din[31]}} << (6'd32-{1'b0,s}));
 
    //opcode_ror: dout = not yet implemented
 
    default: dout = din << s;
 
    endcase
 
end
end
endgenerate
endgenerate
endmodule
endmodule
// logic unit
// logic unit
// supporting the following logic functions
// supporting the following logic functions

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