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Line 68... Line 68...
// output active high global reset sync with two DFFs 
// output active high global reset sync with two DFFs 
`timescale 1 ns/100 ps
`timescale 1 ns/100 ps
module vl_sync_rst ( rst_n_i, rst_o, clk);
module vl_sync_rst ( rst_n_i, rst_o, clk);
input rst_n_i, clk;
input rst_n_i, clk;
output rst_o;
output rst_o;
reg [0:1] tmp;
reg [1:0] tmp;
always @ (posedge clk or negedge rst_n_i)
always @ (posedge clk or negedge rst_n_i)
if (!rst_n_i)
if (!rst_n_i)
        tmp <= 2'b11;
        tmp <= 2'b11;
else
else
        tmp <= {1'b0,tmp[0]};
        tmp <= {1'b0,tmp[0]};
Line 205... Line 205...
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
module dff ( d, q, clk, rst);
module vl_dff ( d, q, clk, rst);
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = 0;
        input [width-1:0] d;
        input [width-1:0] d;
        input clk, rst;
        input clk, rst;
        output reg [width-1:0] q;
        output reg [width-1:0] q;
Line 217... Line 217...
        if (rst)
        if (rst)
                q <= reset_value;
                q <= reset_value;
        else
        else
                q <= d;
                q <= d;
endmodule
endmodule
module dff_array ( d, q, clk, rst);
module vl_dff_array ( d, q, clk, rst);
        parameter width = 1;
        parameter width = 1;
        parameter depth = 2;
        parameter depth = 2;
        parameter reset_value = 1'b0;
        parameter reset_value = 1'b0;
        input [width-1:0] d;
        input [width-1:0] d;
        input clk, rst;
        input clk, rst;
Line 237... Line 237...
            for (i=1;i<depth;i=i+1)
            for (i=1;i<depth;i=i+1)
                q_tmp[i] <= q_tmp[i-1];
                q_tmp[i] <= q_tmp[i-1];
        end
        end
    assign q = q_tmp[depth-1];
    assign q = q_tmp[depth-1];
endmodule
endmodule
module dff_ce ( d, ce, q, clk, rst);
module vl_dff_ce ( d, ce, q, clk, rst);
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = 0;
        input [width-1:0] d;
        input [width-1:0] d;
        input ce, clk, rst;
        input ce, clk, rst;
        output reg [width-1:0] q;
        output reg [width-1:0] q;
Line 250... Line 250...
                q <= reset_value;
                q <= reset_value;
        else
        else
                if (ce)
                if (ce)
                        q <= d;
                        q <= d;
endmodule
endmodule
module dff_ce_clear ( d, ce, clear, q, clk, rst);
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = 0;
        input [width-1:0] d;
        input [width-1:0] d;
        input ce, clear, clk, rst;
        input ce, clear, clk, rst;
        output reg [width-1:0] q;
        output reg [width-1:0] q;
Line 266... Line 266...
                if (clear)
                if (clear)
                    q <= {width{1'b0}};
                    q <= {width{1'b0}};
                else
                else
                    q <= d;
                    q <= d;
endmodule
endmodule
module dff_sr ( aclr, aset, clock, data, q);
module vl_dff_sr ( aclr, aset, clock, data, q);
    input         aclr;
    input         aclr;
    input         aset;
    input         aset;
    input         clock;
    input         clock;
    input         data;
    input         data;
    output reg    q;
    output reg    q;
Line 292... Line 292...
     if (direction_clr)
     if (direction_clr)
       direction <= going_empty;
       direction <= going_empty;
     else
     else
       direction <= going_full;*/
       direction <= going_full;*/
endmodule
endmodule
module shreg ( d, q, clk, rst);
module vl_shreg ( d, q, clk, rst);
parameter depth = 10;
parameter depth = 10;
input d;
input d;
output q;
output q;
input clk, rst;
input clk, rst;
reg [1:depth] dffs;
reg [1:depth] dffs;
Line 305... Line 305...
    dffs <= {depth{1'b0}};
    dffs <= {depth{1'b0}};
else
else
    dffs <= {d,dffs[1:depth-1]};
    dffs <= {d,dffs[1:depth-1]};
assign q = dffs[depth];
assign q = dffs[depth];
endmodule
endmodule
module shreg_ce ( d, ce, q, clk, rst);
module vl_shreg_ce ( d, ce, q, clk, rst);
parameter depth = 10;
parameter depth = 10;
input d, ce;
input d, ce;
output q;
output q;
input clk, rst;
input clk, rst;
reg [1:depth] dffs;
reg [1:depth] dffs;
Line 319... Line 319...
else
else
    if (ce)
    if (ce)
        dffs <= {d,dffs[1:depth-1]};
        dffs <= {d,dffs[1:depth-1]};
assign q = dffs[depth];
assign q = dffs[depth];
endmodule
endmodule
module delay ( d, q, clk, rst);
module vl_delay ( d, q, clk, rst);
parameter depth = 10;
parameter depth = 10;
input d;
input d;
output q;
output q;
input clk, rst;
input clk, rst;
reg [1:depth] dffs;
reg [1:depth] dffs;
Line 332... Line 332...
    dffs <= {depth{1'b0}};
    dffs <= {depth{1'b0}};
else
else
    dffs <= {d,dffs[1:depth-1]};
    dffs <= {d,dffs[1:depth-1]};
assign q = dffs[depth];
assign q = dffs[depth];
endmodule
endmodule
module delay_emptyflag ( d, q, emptyflag, clk, rst);
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
parameter depth = 10;
parameter depth = 10;
input d;
input d;
output q, emptyflag;
output q, emptyflag;
input clk, rst;
input clk, rst;
reg [1:depth] dffs;
reg [1:depth] dffs;
Line 348... Line 348...
assign q = dffs[depth];
assign q = dffs[depth];
assign emptyflag = !(|dffs);
assign emptyflag = !(|dffs);
endmodule
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
 
////  Logic functions                                             ////
 
////                                                              ////
 
////  Description                                                 ////
 
////  Logic functions such as multiplexers                        ////
 
////                                                              ////
 
////                                                              ////
 
////  To Do:                                                      ////
 
////   -                                                          ////
 
////                                                              ////
 
////  Author(s):                                                  ////
 
////      - Michael Unneback, unneback@opencores.org              ////
 
////        ORSoC AB                                              ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
 
////                                                              ////
 
//// This source file may be used and distributed without         ////
 
//// restriction provided that this copyright statement is not    ////
 
//// removed from the file and that any derivative work contains  ////
 
//// the original copyright notice and the associated disclaimer. ////
 
////                                                              ////
 
//// This source file is free software; you can redistribute it   ////
 
//// and/or modify it under the terms of the GNU Lesser General   ////
 
//// Public License as published by the Free Software Foundation; ////
 
//// either version 2.1 of the License, or (at your option) any   ////
 
//// later version.                                               ////
 
////                                                              ////
 
//// This source is distributed in the hope that it will be       ////
 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
 
//// details.                                                     ////
 
////                                                              ////
 
//// You should have received a copy of the GNU Lesser General    ////
 
//// Public License along with this source; if not, download it   ////
 
//// from http://www.opencores.org/lgpl.shtml                     ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
 
parameter width = 32;
 
parameter nr_of_ports = 4;
 
input [width-1:0] a3, a2, a1, a0;
 
input [nr_of_ports-1:0] sel;
 
output reg [width-1:0] dout;
 
reg [width-1:0] tmp [nr_of_ports-1:0];
 
integer i;
 
// and
 
assign tmp[0] = {width{sel[0]}} & a0;
 
assign tmp[1] = {width{sel[1]}} & a1;
 
assign tmp[2] = {width{sel[2]}} & a2;
 
assign tmp[3] = {width{sel[3]}} & a3;
 
// or
 
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
 
endmodule
 
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
 
parameter width = 32;
 
parameter nr_of_ports = 5;
 
input [width-1:0] a4, a3, a2, a1, a0;
 
input [nr_of_ports-1:0] sel;
 
output reg [width-1:0] dout;
 
reg [width-1:0] tmp [nr_of_ports-1:0];
 
integer i;
 
// and
 
assign tmp[0] = {width{sel[0]}} & a0;
 
assign tmp[1] = {width{sel[1]}} & a1;
 
assign tmp[2] = {width{sel[2]}} & a2;
 
assign tmp[3] = {width{sel[3]}} & a3;
 
assign tmp[4] = {width{sel[4]}} & a4;
 
// or
 
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
 
endmodule
 
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
 
parameter width = 32;
 
parameter nr_of_ports = 6;
 
input [width-1:0] a5, a4, a3, a2, a1, a0;
 
input [nr_of_ports-1:0] sel;
 
output reg [width-1:0] dout;
 
reg [width-1:0] tmp [nr_of_ports-1:0];
 
integer i;
 
// and
 
assign tmp[0] = {width{sel[0]}} & a0;
 
assign tmp[1] = {width{sel[1]}} & a1;
 
assign tmp[2] = {width{sel[2]}} & a2;
 
assign tmp[3] = {width{sel[3]}} & a3;
 
assign tmp[4] = {width{sel[4]}} & a4;
 
assign tmp[5] = {width{sel[5]}} & a5;
 
// or
 
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
 
endmodule
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////  counter                                                     ////
Line 388... Line 480...
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// binary counter
// binary counter
module cnt_bin_ce ( cke, q, rst, clk);
module vl_cnt_bin_ce ( cke, q, rst, clk);
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   output [length:1] q;
   output [length:1] q;
   input rst;
   input rst;
   input clk;
   input clk;
Line 451... Line 543...
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// binary counter
// binary counter
module cnt_bin_ce_clear ( clear, cke, q, rst, clk);
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
   parameter length = 4;
   parameter length = 4;
   input clear;
   input clear;
   input cke;
   input cke;
   output [length:1] q;
   output [length:1] q;
   input rst;
   input rst;
Line 515... Line 607...
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// binary counter
// binary counter
module cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
   parameter length = 4;
   parameter length = 4;
   input clear;
   input clear;
   input set;
   input set;
   input cke;
   input cke;
   input rew;
   input rew;
Line 583... Line 675...
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// binary counter
// binary counter
module cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   input rew;
   input rew;
   output reg level1;
   output reg level1;
   input rst;
   input rst;
Line 657... Line 749...
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// LFSR counter
// LFSR counter
module cnt_lfsr_zq ( zq, rst, clk);
module vl_cnt_lfsr_zq ( zq, rst, clk);
   parameter length = 4;
   parameter length = 4;
   output reg zq;
   output reg zq;
   input rst;
   input rst;
   input clk;
   input clk;
   parameter clear_value = 0;
   parameter clear_value = 0;
Line 767... Line 859...
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// LFSR counter
// LFSR counter
module cnt_lfsr_ce_zq ( cke, zq, rst, clk);
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   output reg zq;
   output reg zq;
   input rst;
   input rst;
   input clk;
   input clk;
Line 880... Line 972...
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// LFSR counter
// LFSR counter
module cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   input rew;
   input rew;
   output reg level1;
   output reg level1;
   input rst;
   input rst;
Line 1045... Line 1137...
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// GRAY counter
// GRAY counter
module cnt_gray ( q, rst, clk);
module vl_cnt_gray ( q, rst, clk);
   parameter length = 4;
   parameter length = 4;
   output reg [length:1] q;
   output reg [length:1] q;
   input rst;
   input rst;
   input clk;
   input clk;
   parameter clear_value = 0;
   parameter clear_value = 0;
Line 1110... Line 1202...
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// GRAY counter
// GRAY counter
module cnt_gray_ce ( cke, q, rst, clk);
module vl_cnt_gray_ce ( cke, q, rst, clk);
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   output reg [length:1] q;
   output reg [length:1] q;
   input rst;
   input rst;
   input clk;
   input clk;
Line 1178... Line 1270...
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// GRAY counter
// GRAY counter
module cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   output reg [length:1] q;
   output reg [length:1] q;
   output [length:1] q_bin;
   output [length:1] q_bin;
   input rst;
   input rst;
Line 1247... Line 1339...
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
module cnt_shreg_wrap ( q, rst, clk);
module vl_cnt_shreg_wrap ( q, rst, clk);
   parameter length = 4;
   parameter length = 4;
   output reg [0:length-1] q;
   output reg [0:length-1] q;
   input rst;
   input rst;
   input clk;
   input clk;
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        q <= {1'b1,{length-1{1'b0}}};
        q <= {1'b1,{length-1{1'b0}}};
    else
    else
        q <= {q[length-1],q[0:length-2]};
        q <= {q[length-1],q[0:length-2]};
endmodule
endmodule
module cnt_shreg_ce_wrap ( cke, q, rst, clk);
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   output reg [0:length-1] q;
   output reg [0:length-1] q;
   input rst;
   input rst;
   input clk;
   input clk;
Line 1271... Line 1363...
        q <= {1'b1,{length-1{1'b0}}};
        q <= {1'b1,{length-1{1'b0}}};
    else
    else
        if (cke)
        if (cke)
            q <= {q[length-1],q[0:length-2]};
            q <= {q[length-1],q[0:length-2]};
endmodule
endmodule
module cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
   parameter length = 4;
   parameter length = 4;
   input cke, clear;
   input cke, clear;
   output reg [0:length-1] q;
   output reg [0:length-1] q;
   input rst;
   input rst;
   input clk;
   input clk;
Line 1287... Line 1379...
            if (clear)
            if (clear)
                q <= {1'b1,{length-1{1'b0}}};
                q <= {1'b1,{length-1{1'b0}}};
            else
            else
                q <= q >> 1;
                q <= q >> 1;
endmodule
endmodule
module cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
   parameter length = 4;
   parameter length = 4;
   input cke, clear;
   input cke, clear;
   output reg [0:length-1] q;
   output reg [0:length-1] q;
   input rst;
   input rst;
   input clk;
   input clk;
Line 1579... Line 1671...
         {Q3,Q2} : direction_clr <= 1'b1;
         {Q3,Q2} : direction_clr <= 1'b1;
         {Q4,Q3} : direction_clr <= 1'b1;
         {Q4,Q3} : direction_clr <= 1'b1;
         {Q1,Q4} : direction_clr <= 1'b1;
         {Q1,Q4} : direction_clr <= 1'b1;
         default : direction_clr <= 1'b0;
         default : direction_clr <= 1'b0;
       endcase
       endcase
    dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
   assign async_empty = (wptr == rptr) && (direction==going_empty);
   assign async_empty = (wptr == rptr) && (direction==going_empty);
   assign async_full  = (wptr == rptr) && (direction==going_full);
   assign async_full  = (wptr == rptr) && (direction==going_full);
    dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
    dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
/*
/*
   always @ (posedge wclk or posedge rst or posedge async_full)
   always @ (posedge wclk or posedge rst or posedge async_full)
     if (rst)
     if (rst)
       {fifo_full, fifo_full2} <= 2'b00;
       {fifo_full, fifo_full2} <= 2'b00;
     else if (async_full)
     else if (async_full)
Line 1598... Line 1690...
/*   always @ (posedge rclk or posedge async_empty)
/*   always @ (posedge rclk or posedge async_empty)
     if (async_empty)
     if (async_empty)
       {fifo_empty, fifo_empty2} <= 2'b11;
       {fifo_empty, fifo_empty2} <= 2'b11;
     else
     else
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
    dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
    dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
endmodule // async_comp
endmodule // async_comp
module vl_fifo_1r1w_async (
module vl_fifo_1r1w_async (
    d, wr, fifo_full, wr_clk, wr_rst,
    d, wr, fifo_full, wr_clk, wr_rst,
    q, rd, fifo_empty, rd_clk, rd_rst
    q, rd, fifo_empty, rd_clk, rd_rst
    );
    );
Line 1624... Line 1716...
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
vl_fifo_1r1w_async (
vl_fifo_1r1w_async (
    d, wr, fifo_full, wr_clk, wr_rst,
    d, wr, fifo_full, wr_clk, wr_rst,
    q, rd, fifo_empty, rd_clk, rd_rst
    q, rd, fifo_empty, rd_clk, rd_rst
    );
    );
cnt_gray_ce_bin
vl_cnt_gray_ce_bin
    # ( .length(addr_width))
    # ( .length(addr_width))
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
cnt_gray_ce_bin
vl_cnt_gray_ce_bin
    # (.length(addr_width))
    # (.length(addr_width))
    fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
    fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
vl_dpram_1r1w
vl_dpram_1r1w
    # (.data_width(data_width), .addr_width(addr_width))
    # (.data_width(data_width), .addr_width(addr_width))
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
Line 1713... Line 1805...
// adr_gen
// adr_gen
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
// dpram
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
cnt_gray_ce_bin
vl_cnt_gray_ce_bin
    # ( .length(addr_width))
    # ( .length(addr_width))
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
cnt_gray_ce_bin
vl_cnt_gray_ce_bin
    # (.length(addr_width))
    # (.length(addr_width))
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
cnt_gray_ce_bin
vl_cnt_gray_ce_bin
    # ( .length(addr_width))
    # ( .length(addr_width))
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
cnt_gray_ce_bin
vl_cnt_gray_ce_bin
    # (.length(addr_width))
    # (.length(addr_width))
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
// mux read or write adr to DPRAM
// mux read or write adr to DPRAM
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
Line 1782... Line 1874...
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// async wb3 - wb3 bridge
// async wb3 - wb3 bridge
`timescale 1ns/1ns
`timescale 1ns/1ns
module wb3wb3_bridge (
module vl_wb3wb3_bridge (
        // wishbone slave side
        // wishbone slave side
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
        // wishbone master side
        // wishbone master side
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
input [31:0] wbs_dat_i;
input [31:0] wbs_dat_i;
Line 1843... Line 1935...
else
else
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
                wbs_eoc <= wbs_bte_i==linear;
                wbs_eoc <= wbs_bte_i==linear;
        else if (wbs_eoc_alert & (a_rd | a_wr))
        else if (wbs_eoc_alert & (a_rd | a_wr))
                wbs_eoc <= 1'b1;
                wbs_eoc <= 1'b1;
cnt_shreg_ce_clear # ( .length(16))
vl_cnt_shreg_ce_clear # ( .length(16))
    cnt0 (
    cnt0 (
        .cke(wbs_ack_o),
        .cke(wbs_ack_o),
        .clear(wbs_eoc),
        .clear(wbs_eoc),
        .q(wbs_count),
        .q(wbs_count),
        .rst(wbs_rst),
        .rst(wbs_rst),
Line 1902... Line 1994...
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
                   1'b0;
                   1'b0;
assign b_rd = b_rd_adr | b_rd_data;
assign b_rd = b_rd_adr | b_rd_data;
dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
cnt_shreg_ce_clear # ( .length(16))
vl_cnt_shreg_ce_clear # ( .length(16))
    cnt1 (
    cnt1 (
        .cke(wbm_ack_i),
        .cke(wbm_ack_i),
        .clear(wbm_eoc),
        .clear(wbm_eoc),
        .q(wbm_count),
        .q(wbm_count),
        .rst(wbm_rst),
        .rst(wbm_rst),
Line 1950... Line 2042...
    .b_clk(wbm_clk),
    .b_clk(wbm_clk),
    .b_rst(wbm_rst)
    .b_rst(wbm_rst)
    );
    );
endmodule
endmodule
// WB ROM
// WB ROM
module wb_boot_rom (
module vl_wb_boot_rom (
    wb_adr_i, wb_stb_i, wb_cyc_i,
    wb_adr_i, wb_stb_i, wb_cyc_i,
    wb_dat_o, wb_ack_o, wb_clk, wb_rst);
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
 
    parameter adr_hi = 31;
 
    parameter adr_lo = 28;
 
    parameter adr_sel = 4'hf;
 
    parameter addr_width = 5;
`ifndef BOOT_ROM
`ifndef BOOT_ROM
`define BOOT_ROM "boot_rom.v"
`define BOOT_ROM "boot_rom.v"
`endif
`endif
    parameter addr_width = 5;
    input [adr_hi:2]    wb_adr_i;
   input [(addr_width+2)-1:2]       wb_adr_i;
 
   input                            wb_stb_i;
   input                            wb_stb_i;
   input                            wb_cyc_i;
   input                            wb_cyc_i;
   output reg [31:0]                 wb_dat_o;
    output [31:0]        wb_dat_o;
   output reg                       wb_ack_o;
    output              wb_ack_o;
 
    output              hit_o;
   input                            wb_clk;
   input                            wb_clk;
   input                            wb_rst;
   input                            wb_rst;
 
    wire hit;
 
    reg [31:0] wb_dat;
 
    reg wb_ack;
 
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
always @ (posedge wb_clk or posedge wb_rst)
always @ (posedge wb_clk or posedge wb_rst)
    if (wb_rst)
    if (wb_rst)
        wb_dat_o <= 32'h15000000;
        wb_dat <= 32'h15000000;
    else
    else
         case (wb_adr_i)
         case (wb_adr_i[addr_width-1:2])
`include `BOOT_ROM
`include `BOOT_ROM
           /*
           /*
            // Zero r0 and jump to 0x00000100
            // Zero r0 and jump to 0x00000100
            0 : wb_dat_o <= 32'h18000000;
            0 : wb_dat <= 32'h18000000;
            1 : wb_dat_o <= 32'hA8200000;
            1 : wb_dat <= 32'hA8200000;
            2 : wb_dat_o <= 32'hA8C00100;
            2 : wb_dat <= 32'hA8C00100;
            3 : wb_dat_o <= 32'h44003000;
            3 : wb_dat <= 32'h44003000;
            4 : wb_dat_o <= 32'h15000000;
            4 : wb_dat <= 32'h15000000;
            */
            */
           default:
           default:
             wb_dat_o <= 32'h00000000;
             wb_dat <= 32'h00000000;
         endcase // case (wb_adr_i)
         endcase // case (wb_adr_i)
always @ (posedge wb_clk or posedge wb_rst)
always @ (posedge wb_clk or posedge wb_rst)
    if (wb_rst)
    if (wb_rst)
        wb_ack_o <= 1'b0;
        wb_ack <= 1'b0;
    else
    else
        wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
 
assign hit_o = hit;
 
assign wb_dat_o = wb_dat & {32{wb_ack}};
 
assign wb_ack_o = wb_ack;
 
endmodule
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
////  Arithmetic functions                                        ////
 
////                                                              ////
 
////  Description                                                 ////
 
////  Arithmetic functions for ALU and DSP                        ////
 
////                                                              ////
 
////                                                              ////
 
////  To Do:                                                      ////
 
////   -                                                          ////
 
////                                                              ////
 
////  Author(s):                                                  ////
 
////      - Michael Unneback, unneback@opencores.org              ////
 
////        ORSoC AB                                              ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
 
////                                                              ////
 
//// This source file may be used and distributed without         ////
 
//// restriction provided that this copyright statement is not    ////
 
//// removed from the file and that any derivative work contains  ////
 
//// the original copyright notice and the associated disclaimer. ////
 
////                                                              ////
 
//// This source file is free software; you can redistribute it   ////
 
//// and/or modify it under the terms of the GNU Lesser General   ////
 
//// Public License as published by the Free Software Foundation; ////
 
//// either version 2.1 of the License, or (at your option) any   ////
 
//// later version.                                               ////
 
////                                                              ////
 
//// This source is distributed in the hope that it will be       ////
 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
 
//// details.                                                     ////
 
////                                                              ////
 
//// You should have received a copy of the GNU Lesser General    ////
 
//// Public License along with this source; if not, download it   ////
 
//// from http://www.opencores.org/lgpl.shtml                     ////
 
////                                                              ////
 
//////////////////////////////////////////////////////////////////////
 
// signed multiplication
 
module vl_mults (a,b,p);
 
parameter operand_a_width = 18;
 
parameter operand_b_width = 18;
 
parameter result_hi = 35;
 
parameter result_lo = 0;
 
input [operand_a_width-1:0] a;
 
input [operand_b_width-1:0] b;
 
output [result_hi:result_lo] p;
 
wire signed [operand_a_width-1:0] ai;
 
wire signed [operand_b_width-1:0] bi;
 
wire signed [operand_a_width+operand_b_width-1:0] result;
 
    assign ai = a;
 
    assign bi = b;
 
    assign result = ai * bi;
 
    assign p = result[result_hi:result_lo];
 
endmodule
 
module vl_mults18x18 (a,b,p);
 
input [17:0] a,b;
 
output [35:0] p;
 
vl_mult
 
    # (.operand_a_width(18), .operand_b_width(18))
 
    mult0 (.a(a), .b(b), .p(p));
 
endmodule
 
// unsigned multiplication
 
module vl_mult (a,b,p);
 
parameter operand_a_width = 18;
 
parameter operand_b_width = 18;
 
parameter result_hi = 35;
 
parameter result_lo = 0;
 
input [operand_a_width-1:0] a;
 
input [operand_b_width-1:0] b;
 
output [result_hi:result_hi] p;
 
wire [operand_a_width+operand_b_width-1:0] result;
 
    assign result = a * b;
 
    assign p = result[result_hi:result_lo];
 
endmodule
 
// shift unit
 
// supporting the following shift functions
 
//   SLL
 
//   SRL
 
//   SRA
 
module vl_shift_unit_32( din, s, dout, opcode);
 
input [31:0] din; // data in operand
 
input [4:0] s; // shift operand
 
input [1:0] opcode;
 
output [31:0] dout;
 
parameter opcode_sll = 2'b00;
 
//parameter opcode_srl = 2'b01;
 
parameter opcode_sra = 2'b10;
 
//parameter opcode_ror = 2'b11;
 
wire sll, sra;
 
assign sll = opcode == opcode_sll;
 
assign sra = opcode == opcode_sra;
 
wire [15:1] s1;
 
wire [3:0] sign;
 
wire [7:0] tmp [0:3];
 
// first stage is multiplier based
 
// shift operand as fractional 8.7
 
assign s1[15] = sll & s[2:0]==3'd7;
 
assign s1[14] = sll & s[2:0]==3'd6;
 
assign s1[13] = sll & s[2:0]==3'd5;
 
assign s1[12] = sll & s[2:0]==3'd4;
 
assign s1[11] = sll & s[2:0]==3'd3;
 
assign s1[10] = sll & s[2:0]==3'd2;
 
assign s1[ 9] = sll & s[2:0]==3'd1;
 
assign s1[ 8] = s[2:0]==3'd0;
 
assign s1[ 7] = !sll & s[2:0]==3'd1;
 
assign s1[ 6] = !sll & s[2:0]==3'd2;
 
assign s1[ 5] = !sll & s[2:0]==3'd3;
 
assign s1[ 4] = !sll & s[2:0]==3'd4;
 
assign s1[ 3] = !sll & s[2:0]==3'd5;
 
assign s1[ 2] = !sll & s[2:0]==3'd6;
 
assign s1[ 1] = !sll & s[2:0]==3'd7;
 
assign sign[3] = din[31] & sra;
 
assign sign[2] = sign[3] & (&din[31:24]);
 
assign sign[1] = sign[2] & (&din[23:16]);
 
assign sign[0] = sign[1] & (&din[15:8]);
 
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
 
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
 
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
 
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
 
// second stage is multiplexer based
 
// shift on byte level
 
// mux byte 3
 
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
 
                     (sll & s[4:3]==2'b01) ? tmp[2] :
 
                     (sll & s[4:3]==2'b10) ? tmp[1] :
 
                     (sll & s[4:3]==2'b11) ? tmp[0] :
 
                     {8{sign[3]}};
 
// mux byte 2
 
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
 
                     (sll & s[4:3]==2'b01) ? tmp[1] :
 
                     (sll & s[4:3]==2'b10) ? tmp[0] :
 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
 
                     (s[4:3]==2'b01) ? tmp[3] :
 
                     {8{sign[3]}};
 
// mux byte 1
 
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
 
                     (sll & s[4:3]==2'b01) ? tmp[0] :
 
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
 
                     (s[4:3]==2'b01) ? tmp[2] :
 
                     (s[4:3]==2'b10) ? tmp[3] :
 
                     {8{sign[3]}};
 
// mux byte 0
 
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
 
                     (sll) ?  {8{1'b0}}:
 
                     (s[4:3]==2'b01) ? tmp[1] :
 
                     (s[4:3]==2'b10) ? tmp[2] :
 
                     tmp[3];
 
endmodule
 
// logic unit
 
// supporting the following logic functions
 
//    a and b
 
//    a or  b
 
//    a xor b
 
//    not b
 
module vl_logic_unit( a, b, result, opcode);
 
parameter width = 32;
 
parameter opcode_and = 2'b00;
 
parameter opcode_or  = 2'b01;
 
parameter opcode_xor = 2'b10;
 
input [width-1:0] a,b;
 
output [width-1:0] result;
 
input [1:0] opcode;
 
assign result = (opcode==opcode_and) ? a & b :
 
                (opcode==opcode_or)  ? a | b :
 
                (opcode==opcode_xor) ? a ^ b :
 
                b;
 
endmodule
 
module vl_arith_unit ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
 
parameter width = 32;
 
parameter opcode_add = 1'b0;
 
parameter opcode_sub = 1'b1;
 
input [width-1:0] a,b;
 
input c_in, add_sub, sign;
 
output [width-1:0] result;
 
output c_out, z, ovfl;
 
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
 
assign z = (result=={width{1'b0}});
 
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
 
               (~a[width-1] & ~b[width-1] &  result[width-1]);
endmodule
endmodule
 
 
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