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https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
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Line 266... |
if (clear)
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if (clear)
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q <= {width{1'b0}};
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q <= {width{1'b0}};
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else
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else
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q <= d;
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q <= d;
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endmodule
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endmodule
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module vl_dff_ce_set ( d, ce, set, q, clk, rst);
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parameter width = 1;
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parameter reset_value = 0;
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input [width-1:0] d;
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input ce, set, clk, rst;
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output reg [width-1:0] q;
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always @ (posedge clk or posedge rst)
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if (rst)
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q <= reset_value;
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else
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if (ce)
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if (set)
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q <= {width{1'b1}};
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else
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q <= d;
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endmodule
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module vl_dff_sr ( aclr, aset, clock, data, q);
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module vl_dff_sr ( aclr, aset, clock, data, q);
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input aclr;
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input aclr;
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input aset;
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input aset;
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input clock;
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input clock;
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input data;
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input data;
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